[PATCH 05/12] drm/msm/disp: simplify tiled RGB{,A,X} formats definitions
Dmitry Baryshkov
dmitry.baryshkov at oss.qualcomm.com
Sat Jul 5 02:47:26 UTC 2025
Define several additional macros, capturing tiled RGB format classes, in
order to simplify defining particular RGB* format.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at oss.qualcomm.com>
---
drivers/gpu/drm/msm/disp/mdp_format.c | 118 ++++++++++++++++++++++++----------
1 file changed, 85 insertions(+), 33 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/mdp_format.c b/drivers/gpu/drm/msm/disp/mdp_format.c
index 28cef986f2d662484afd47440a79393c48256ff5..d577b3d53fbebced63792b5c65f50dd45211c8ea 100644
--- a/drivers/gpu/drm/msm/disp/mdp_format.c
+++ b/drivers/gpu/drm/msm/disp/mdp_format.c
@@ -163,22 +163,83 @@ static struct csc_cfg csc_convert[CSC_MAX] = {
.tile_height = MDP_TILE_HEIGHT_DEFAULT \
}
-#define INTERLEAVED_RGB_FMT_TILED(fmt, a, r, g, b, e0, e1, e2, e3, uc, \
-alpha, bp, flg) \
+#define INTERLEAVED_RGB_FMT_TILED(fmt, bp, r, g, b, e0, e1, e2) \
{ \
.pixel_format = DRM_FORMAT_ ## fmt, \
.fetch_type = MDP_PLANE_INTERLEAVED, \
- .alpha_enable = alpha, \
+ .alpha_enable = false, \
+ .element = { (e0), (e1), (e2), 0 }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = 0, \
+ .chroma_sample = CHROMA_FULL, \
+ .unpack_count = 3, \
+ .bpp = bp, \
+ .fetch_mode = MDP_FETCH_UBWC, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ MSM_FORMAT_FLAG_COMPRESSED, \
+ .num_planes = 2, \
+ .tile_height = MDP_TILE_HEIGHT_UBWC, \
+}
+
+#define INTERLEAVED_RGBA_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .alpha_enable = true, \
.element = { (e0), (e1), (e2), (e3) }, \
.bpc_g_y = g, \
.bpc_b_cb = b, \
.bpc_r_cr = r, \
.bpc_a = a, \
.chroma_sample = CHROMA_FULL, \
- .unpack_count = uc, \
+ .unpack_count = 4, \
.bpp = bp, \
.fetch_mode = MDP_FETCH_UBWC, \
- .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | flg, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ MSM_FORMAT_FLAG_COMPRESSED, \
+ .num_planes = 2, \
+ .tile_height = MDP_TILE_HEIGHT_UBWC, \
+}
+
+#define INTERLEAVED_RGBX_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .alpha_enable = false, \
+ .element = { (e0), (e1), (e2), (e3) }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = CHROMA_FULL, \
+ .unpack_count = 4, \
+ .bpp = bp, \
+ .fetch_mode = MDP_FETCH_UBWC, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ MSM_FORMAT_FLAG_COMPRESSED, \
+ .num_planes = 2, \
+ .tile_height = MDP_TILE_HEIGHT_UBWC, \
+}
+
+#define INTERLEAVED_RGBA_DX_FMT_TILED(fmt, bp, a, r, g, b, e0, e1, e2, e3) \
+{ \
+ .pixel_format = DRM_FORMAT_ ## fmt, \
+ .fetch_type = MDP_PLANE_INTERLEAVED, \
+ .alpha_enable = true, \
+ .element = { (e0), (e1), (e2), (e3) }, \
+ .bpc_g_y = g, \
+ .bpc_b_cb = b, \
+ .bpc_r_cr = r, \
+ .bpc_a = a, \
+ .chroma_sample = CHROMA_FULL, \
+ .unpack_count = 4, \
+ .bpp = bp, \
+ .fetch_mode = MDP_FETCH_UBWC, \
+ .flags = MSM_FORMAT_FLAG_UNPACK_TIGHT | \
+ MSM_FORMAT_FLAG_DX | \
+ MSM_FORMAT_FLAG_COMPRESSED, \
.num_planes = 2, \
.tile_height = MDP_TILE_HEIGHT_UBWC, \
}
@@ -525,58 +586,49 @@ static const struct msm_format mdp_formats[] = {
* the data will be passed by user-space.
*/
static const struct msm_format mdp_formats_ubwc[] = {
- INTERLEAVED_RGB_FMT_TILED(BGR565,
- 0, BPC5, BPC6, BPC5,
- C2_R_Cr, C0_G_Y, C1_B_Cb, 0, 3,
- false, 2, MSM_FORMAT_FLAG_COMPRESSED),
+ INTERLEAVED_RGB_FMT_TILED(BGR565, 2,
+ BPC5, BPC6, BPC5,
+ C2_R_Cr, C0_G_Y, C1_B_Cb),
- INTERLEAVED_RGB_FMT_TILED(ABGR8888,
+ INTERLEAVED_RGBA_FMT_TILED(ABGR8888, 4,
BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_COMPRESSED),
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
/* ARGB8888 and ABGR8888 purposely have the same color
* ordering. The hardware only supports ABGR8888 UBWC
* natively.
*/
- INTERLEAVED_RGB_FMT_TILED(ARGB8888,
+ INTERLEAVED_RGBA_FMT_TILED(ARGB8888, 4,
BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_COMPRESSED),
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
- INTERLEAVED_RGB_FMT_TILED(XBGR8888,
+ INTERLEAVED_RGBX_FMT_TILED(XBGR8888, 4,
BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, MSM_FORMAT_FLAG_COMPRESSED),
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
- INTERLEAVED_RGB_FMT_TILED(XRGB8888,
+ INTERLEAVED_RGBX_FMT_TILED(XRGB8888, 4,
BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- false, 4, MSM_FORMAT_FLAG_COMPRESSED),
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
- INTERLEAVED_RGB_FMT_TILED(ABGR2101010,
+ INTERLEAVED_RGBA_DX_FMT_TILED(ABGR2101010, 4,
BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
- INTERLEAVED_RGB_FMT_TILED(XBGR2101010,
+ INTERLEAVED_RGBA_DX_FMT_TILED(XBGR2101010, 4,
BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
- INTERLEAVED_RGB_FMT_TILED(XRGB2101010,
+ INTERLEAVED_RGBA_DX_FMT_TILED(XRGB2101010, 4,
BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
/* XRGB2101010 and ARGB2101010 purposely have the same color
* ordering. The hardware only supports ARGB2101010 UBWC
* natively.
*/
- INTERLEAVED_RGB_FMT_TILED(ARGB2101010,
+ INTERLEAVED_RGBA_DX_FMT_TILED(ARGB2101010, 4,
BPC8A, BPC8, BPC8, BPC8,
- C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA, 4,
- true, 4, MSM_FORMAT_FLAG_DX | MSM_FORMAT_FLAG_COMPRESSED),
+ C2_R_Cr, C0_G_Y, C1_B_Cb, C3_ALPHA),
PSEUDO_YUV_FMT_TILED(NV12,
0, BPC8, BPC8, BPC8,
--
2.39.5
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