[PATCH 2/2] drm: renesas: rz-du: Set DSI divider based on target MIPI device
Sergey Shtylyov
sergei.shtylyov at gmail.com
Thu Jul 10 08:44:58 UTC 2025
On 7/9/25 11:55 PM, Chris Brandt wrote:
> Before the MIPI DSI clock source can be configured, the target divide
> ratio needs to be known.
>
> Signed-off-by: Chris Brandt <chris.brandt at renesas.com>
> ---
> drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> index 4ad0be03a5b4..a8796df43f75 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
[...]
> @@ -666,6 +667,22 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host,
>
> drm_bridge_add(&dsi->bridge);
>
> + /* Report required division ratio setting for the MIPI clock dividers
/* should be on a line of its own (unless you do a networking patch)...
> + * Assume the default clock source is FOUTPOSTDIV (PLL/2) being fed to the DSI-PHY, but also
> + * the DSI-PHY must be 16x the MIPI-DSI HS clock.
> + *
> + * pllclk/2 = vclk * DSI divider
Why no spaces around / while there are spaces around *?
[...]
MBR, Sergey
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