[PATCH v1 3/5] gpu/drm: host1x: mipi: add Tegra20/Tegra30 MIPI calibration logic

[Mikko Perttunen]

On Friday, July 18, 2025 6:17 PM Svyatoslav Ryhel wrote:
> пт, 18 лип. 2025 р. о 12:11 Mikko Perttunen <mperttunen at nvidia.com> пише:
> > On Thursday, July 17, 2025 11:21 PM Svyatoslav Ryhel wrote:
> > > ...
> > > @@ -311,6 +330,43 @@ int tegra_mipi_finish_calibration(struct
> > > tegra_mipi_device *device) }
> > > 
> > >  EXPORT_SYMBOL(tegra_mipi_finish_calibration);
> > > 
> > > +static int tegra20_mipi_calibration(struct tegra_mipi_device *device)
> > > +{
> > > +     struct tegra_mipi *mipi = device->mipi;
> > > +     const struct tegra_mipi_soc *soc = mipi->soc;
> > > +     u32 value;
> > > +     int err;
> > > +
> > > +     err = clk_enable(mipi->csi_clk);
> > > +     if (err < 0)
> > > +             return err;
> > > +
> > > +     mutex_lock(&mipi->lock);
> > > +
> > > +     value = MIPI_CAL_CONFIG_TERMOS(soc->termos);
> > > +     tegra_mipi_writel(mipi, value, CSI_CILA_MIPI_CAL_CONFIG);
> > > +
> > > +     value = MIPI_CAL_CONFIG_TERMOS(soc->termos);
> > > +     tegra_mipi_writel(mipi, value, CSI_CILB_MIPI_CAL_CONFIG);
> > > +
> > > +     value = MIPI_CAL_CONFIG_HSPDOS(soc->hspdos) |
> > > +             MIPI_CAL_CONFIG_HSPUOS(soc->hspuos);
> > > +     tegra_mipi_writel(mipi, value, CSI_DSI_MIPI_CAL_CONFIG);
> > > +
> > > +     value = MIPI_CAL_BIAS_PAD_DRV_DN_REF(soc->pad_drive_down_ref) |
> > > +             MIPI_CAL_BIAS_PAD_DRV_UP_REF(soc->pad_drive_up_ref);
> > > +     tegra_mipi_writel(mipi, value, CSI_MIPIBIAS_PAD_CONFIG);
> > > +
> > > +     tegra_mipi_writel(mipi, 0x0, CSI_CIL_PAD_CONFIG);
> > > +
> > > +     mutex_unlock(&mipi->lock);
> > > +
> > > +     clk_disable(mipi->csi_clk);
> > > +     clk_disable(mipi->clk);
> > > +
> > > +     return 0;
> > > +}
> > > +
> > 
> > Where does this sequence come from? It looks a bit strange to me, since it
> > doesn't trigger calibration at all. It would be useful to mention the
> > source in the commit message.
> > 
> > Mikko
> 
> Downstream nvidia sources, 3.1.10 and 3.4, dsi driver, function
> tegra_dsi_pad_calibration

Thanks!

Indeed, looks like for DSI calibration, the HW calibration is never triggered. 
However, for CSI pads, it is. We should take this into account in the device 
tree binding (and driver when CSI support is added) -- the parameter in 
nvidia,mipi-calibrate should specify we're calibrating DSI (probably with an 
enumeration defined in a header file).

Another thing -- the commit subject prefix for gpu/host1x is "gpu: host1x: ", 
and for gpu/drm/tegra "drm/tegra: ".

Cheers,
Mikko