[PATCH] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU

[Neil Armstrong]

On 24/07/2025 16:35, Akhil P Oommen wrote:
> On 7/21/2025 6:05 PM, Neil Armstrong wrote:
>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth along
>> the Frequency and Power Domain level, but by default we leave the
>> OPP core scale the interconnect ddr path.
>>
>> Declare the Bus Control Modules (BCMs) and the corresponding parameters
>> in the GPU info struct to allow the GMU to vote for the bandwidth.
>>
>> Signed-off-by: Neil Armstrong <neil.armstrong at linaro.org>
>> ---
>>   drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> index 00e1afd46b81546eec03e22cda9e9a604f6f3b60..b313505e665ba50e46f2c2b7c34925b929a94c31 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = {
>>   			.pwrup_reglist = &a7xx_pwrup_reglist,
>>   			.gmu_chipid = 0x7050001,
>>   			.gmu_cgc_mode = 0x00020202,
>> +			.bcms = (const struct a6xx_bcm[]) {
>> +				{ .name = "SH0", .buswidth = 16 },
>> +				{ .name = "MC0", .buswidth = 4 },
>> +				{
>> +					.name = "ACV",
>> +					.fixed = true,
>> +					.perfmode = BIT(2),
>> +					.perfmode_bw = 10687500,
> 
> This configurations should be similar to X1-45.

Including the perfmode bit ?

+					.perfmode = BIT(3),
+					.perfmode_bw = 16500000,


Neil

> 
> -Akhil
> 
>> +				},
>> +				{ /* sentinel */ },
>> +			},
>>   		},
>>   		.preempt_record_size = 4192 * SZ_1K,
>>   		.speedbins = ADRENO_SPEEDBINS(
>>
>> ---
>> base-commit: 97987520025658f30bb787a99ffbd9bbff9ffc9d
>> change-id: 20250721-topic-x1e80100-gpu-bwvote-9fc4690fe5e3
>>
>> Best regards,
>