[PATCH v6 07/10] arm64: dts: rockchip: Add DP0 for rk3588

[Sebastian Reichel]

Hi,

On Mon, Jul 28, 2025 at 04:28:32PM +0800, Andy Yan wrote:
> From: Andy Yan <andy.yan at rock-chips.com>
> 
> The DP0 is compliant with the DisplayPort Specification
> Version 1.4, and share the USBDP combo PHY0 with USB 3.1
> HOST0 controller.
> 
> Signed-off-by: Andy Yan <andy.yan at rock-chips.com>
> ---

The description matches the TRM:

Reviewed-by: Sebastian Reichel <sebastian.reichel at collabora.com>

Greetings,

-- Sebastian

> 
> (no changes since v1)
> 
>  arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 30 +++++++++++++++++++
>  1 file changed, 30 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> index 51f11b9c414aa..4a54389c89d75 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
> @@ -1536,6 +1536,36 @@ dsi1_out: port at 1 {
>  		};
>  	};
>  
> +	dp0: dp at fde50000 {
> +		compatible = "rockchip,rk3588-dp";
> +		reg = <0x0 0xfde50000 0x0 0x4000>;
> +		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
> +		clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>,
> +			 <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>,
> +			 <&cru MCLK_SPDIF2_DP0>;
> +		clock-names = "apb", "aux", "hdcp", "i2s", "spdif";
> +		assigned-clocks = <&cru CLK_AUX16M_0>;
> +		assigned-clock-rates = <16000000>;
> +		resets = <&cru SRST_DP0>;
> +		phys = <&usbdp_phy0 PHY_TYPE_DP>;
> +		power-domains = <&power RK3588_PD_VO0>;
> +		#sound-dai-cells = <0>;
> +		status = "disabled";
> +
> +		ports {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			dp0_in: port at 0 {
> +				reg = <0>;
> +			};
> +
> +			dp0_out: port at 1 {
> +				reg = <1>;
> +			};
> +		};
> +	};
> +
>  	hdmi0: hdmi at fde80000 {
>  		compatible = "rockchip,rk3588-dw-hdmi-qp";
>  		reg = <0x0 0xfde80000 0x0 0x20000>;
> -- 
> 2.43.0
> 
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