[PATCH 10/22] pinctrl: sunxi: add missed lvds pins for a100/a133

[Parthiban]

On 6/25/25 3:41 PM, Paul Kocialkowski wrote:
> On Wed 25 Jun 25, 15:06, Parthiban wrote:
>>
>> On 6/25/25 2:16 PM, Paul Kocialkowski wrote:
>>> Hi and thanks for your work!
>>>
>>> On Fri 27 Dec 24, 16:37, Parthiban Nallathambi wrote:
>>>> lvds, lcd, dsi all shares the same GPIO D bank and lvds0
>>>> data 3 lines and lvds1 pins are missed, add them.
>>> Would it also make sense to submit device-tree pin definitions here?
>>
>> this patch is already merged. 
>> git show --stat cef4f1b5ba99a964cd6dd248bb373520573c972f
>> commit cef4f1b5ba99a964cd6dd248bb373520573c972f
>> Author: Parthiban Nallathambi <parthiban at linumiz.com>
>> Date:   Fri Dec 27 16:37:57 2024 +0530
>>
>>     pinctrl: sunxi: add missed lvds pins for a100/a133
>>     
>>     lvds, lcd, dsi all shares the same GPIO D bank and lvds0
>>     data 3 lines and lvds1 pins are missed, add them.
>>     
>>     Signed-off-by: Parthiban Nallathambi <parthiban at linumiz.com>
>>     Link: https://lore.kernel.org/20241227-a133-display-support-v1-10-13b52f71fb14@linumiz.com
>>     Signed-off-by: Linus Walleij <linus.walleij at linaro.org>
>>
>>  drivers/pinctrl/sunxi/pinctrl-sun50i-a100.c | 12 ++++++++++++
>>  1 file changed, 12 insertions(+)
>>
>> Do you mean the consumer/board devicetree changes?
> 
> I mean the pin definitions for lvds in the sun50i-a100.dtsi device-tree.
> 
> But maybe you wanted to submit those after the bindings/driver changes are
> merged?

                pio: pinctrl at 300b000 {
                        compatible = "allwinner,sun50i-a100-pinctrl";
                        reg = <0x0300b000 0x400>;
                        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&ccu CLK_APB1>, <&dcxo24M>, <&osc32k>;
                        clock-names = "apb", "hosc", "losc";
                        gpio-controller;
                        #gpio-cells = <3>;
                        interrupt-controller;
                        #interrupt-cells = <3>;
                        
                        lcd_lvds0_pins: lcd-lvds0-pins {
                                pins = "PD0", "PD1", "PD2", "PD3", "PD4",
                                        "PD5", "PD6", "PD7", "PD8", "PD9";
                                function = "lvds0";
                        };
                        
                        lcd_lvds1_pins: lcd-lvds1-pins {
                                pins = "PD10", "PD11", "PD12", "PD13", "PD14",
                                        "PD15", "PD16", "PD17", "PD18", "PD19";
                                function = "lvds1";
                        };
                        
                        dsi0_pins: dsi0-pins {
                                pins = "PD0", "PD1", "PD2", "PD3", "PD4",
                                        "PD5", "PD6", "PD7", "PD8", "PD9";
                                function = "dsi0";
                        };

                        mmc0_pins: mmc0-pins {
                                pins = "PF0", "PF1", "PF2", "PF3",
                                       "PF4", "PF5";
                                function = "mmc0";
                                drive-strength = <30>;
                                bias-pull-up;
                        };

It got missed when my email server refused to send all the patches.
I will send the revised full patch series after fixing the comments.
Anyways above are the pin definitions.

Thanks,
Parthiban
https://linumiz.com
https://www.linkedin.com/company/linumiz

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> 
> Cheers,
> 
> Paul
>