[PATCH v6 3/4] dt-bindings: display: bridge: renesas,dsi: Add support for RZ/V2H(P) SoC

[Biju Das]

Hi Prabhakar,

Thanks for the patch.

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg at gmail.com>
> Sent: 30 May 2025 18:19
>
> Subject: [PATCH v6 3/4] dt-bindings: display: bridge: renesas,dsi: Add support for RZ/V2H(P) SoC
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> 
> The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of the RZ/G2L SoC. While the
> LINK registers are the same for both SoCs, the D-PHY registers differ. Additionally, the number of
> resets for DSI on
> RZ/V2H(P) is two compared to three on the RZ/G2L.
> 
> To accommodate these differences, a SoC-specific `renesas,r9a09g057-mipi-dsi` compatible string has
> been added for the
> RZ/V2H(P) SoC.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas at glider.be>
> ---
> v5->v6:
> - Preserved the sort order (by part number).
> - Added reviewed tag from Geert.
> 
> v4->v5:
> - No changes
> 
> v3->v4:
> - No changes
> 
> v2->v3:
> - Collected reviewed tag from Krzysztof
> 
> v1->v2:
> - Kept the sort order for schema validation
> - Added  `port at 1: false` for RZ/V2H(P) SoC
> ---
>  .../bindings/display/bridge/renesas,dsi.yaml  | 116 +++++++++++++-----
>  1 file changed, 87 insertions(+), 29 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> index e08c24633926..8c7e2b17ba79 100644
> --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml
> @@ -14,16 +14,17 @@ description: |
>    RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with
>    up to four data lanes.
> 
> -allOf:
> -  - $ref: /schemas/display/dsi-controller.yaml#
> -
>  properties:
>    compatible:
> -    items:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
> +              - renesas,r9a07g054-mipi-dsi # RZ/V2L
> +          - const: renesas,rzg2l-mipi-dsi
> +
>        - enum:
> -          - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC}
> -          - renesas,r9a07g054-mipi-dsi # RZ/V2L
> -      - const: renesas,rzg2l-mipi-dsi
> +          - renesas,r9a09g057-mipi-dsi # RZ/V2H(P)
> 
>    reg:
>      maxItems: 1
> @@ -49,34 +50,56 @@ properties:
>        - const: debug
> 
>    clocks:
> -    items:
> -      - description: DSI D-PHY PLL multiplied clock
> -      - description: DSI D-PHY system clock
> -      - description: DSI AXI bus clock
> -      - description: DSI Register access clock
> -      - description: DSI Video clock
> -      - description: DSI D-PHY Escape mode transmit clock
> +    oneOf:
> +      - items:
> +          - description: DSI D-PHY PLL multiplied clock
> +          - description: DSI D-PHY system clock
> +          - description: DSI AXI bus clock
> +          - description: DSI Register access clock
> +          - description: DSI Video clock
> +          - description: DSI D-PHY Escape mode transmit clock
> +      - items:
> +          - description: DSI D-PHY PLL multiplied clock

This is PLL_Reference_CLK(24 MHz) compared to the DSI D-PHY PLL multiplied clock in RZ/G2L(~3000MHz).

> +          - description: DSI AXI bus clock
> +          - description: DSI Register access clock
> +          - description: DSI Video clock
> +          - description: DSI D-PHY Escape mode transmit clock
> 
>    clock-names:
> -    items:
> -      - const: pllclk
> -      - const: sysclk
> -      - const: aclk
> -      - const: pclk
> -      - const: vclk
> -      - const: lpclk
> +    oneOf:
> +      - items:
> +          - const: pllclk
> +          - const: sysclk
> +          - const: aclk
> +          - const: pclk
> +          - const: vclk
> +          - const: lpclk
> +      - items:
> +          - const: pllclk

pll_ref_clk ??

Cheers,
Biju

> +          - const: aclk
> +          - const: pclk
> +          - const: vclk
> +          - const: lpclk
> 
>    resets:
> -    items:
> -      - description: MIPI_DSI_CMN_RSTB
> -      - description: MIPI_DSI_ARESET_N
> -      - description: MIPI_DSI_PRESET_N
> +    oneOf:
> +      - items:
> +          - description: MIPI_DSI_CMN_RSTB
> +          - description: MIPI_DSI_ARESET_N
> +          - description: MIPI_DSI_PRESET_N
> +      - items:
> +          - description: MIPI_DSI_ARESET_N
> +          - description: MIPI_DSI_PRESET_N
> 
>    reset-names:
> -    items:
> -      - const: rst
> -      - const: arst
> -      - const: prst
> +    oneOf:
> +      - items:
> +          - const: rst
> +          - const: arst
> +          - const: prst
> +      - items:
> +          - const: arst
> +          - const: prst
> 
>    power-domains:
>      maxItems: 1
> @@ -130,6 +153,41 @@ required:
> 
>  additionalProperties: false
> 
> +allOf:
> +  - $ref: ../dsi-controller.yaml#
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: renesas,r9a09g057-mipi-dsi
> +    then:
> +      properties:
> +        clocks:
> +          maxItems: 5
> +
> +        clock-names:
> +          maxItems: 5
> +
> +        resets:
> +          maxItems: 2
> +
> +        reset-names:
> +          maxItems: 2
> +    else:
> +      properties:
> +        clocks:
> +          minItems: 6
> +
> +        clock-names:
> +          minItems: 6
> +
> +        resets:
> +          minItems: 3
> +
> +        reset-names:
> +          minItems: 3
> +
>  examples:
>    - |
>      #include <dt-bindings/clock/r9a07g044-cpg.h>
> --
> 2.49.0