[PATCH] drm/tidss: Set crtc modesetting parameters with adjusted mode

[Michael Walle]

Hi Tomi,

On Tue Jun 24, 2025 at 1:47 PM CEST, Tomi Valkeinen wrote:
> On 24/06/2025 11:04, Jayesh Choudhary wrote:
> > TIDSS uses crtc_* fields to propagate its registers and set the
> > clock rates. So set the CRTC modesetting timing parameters with
> > the adjusted mode when needed, to set correct values.
> > 
> > Cc: Tomi Valkeinen <tomi.valkeinen at ideasonboard.com>
> > Signed-off-by: Jayesh Choudhary <j-choudhary at ti.com>
> > ---
> > 
> > Hello All,
> > 
> > After the DSI fixes[0], TIDSS is using crtc_* timings while programming
> > hardware[1]. But while testing on TI's J784S4-EVM platform, I noticed
> > that crtc_timings are not propagated properly.
> > 
> > The display pipeline there looks like:
> > TIDSS -> CDNS-DSI -> SN65DSI86 bridge -> DisplayPort
> > 
> > Consider the case of 1920x1080 resolution where the EDID mode has clock
> > of 148500kHz. After adjustment, the clock changes to 148800kHz. While
> > this change is reflected in mode->clock, its not propagated to
> > mode->crtc_clock.
>
> Hmm, so CDNS-DSI changes the adjusted_mode->clock, but in the end tidss
> doesn't actually use the adjusted clock at all? I'm pretty sure I tested
> that... I need to try it (and this) again.

FWIW, without this patch, DSI isn't working on my board (DSI -> DSI85
-> eDP). At least without the (now dropped) patch "drm/tidss: Adjust
the pclk based on the HW capabilities" [1].

That is, it was working with v3 of your DSI patch series, but not
with v4. I'll need this patch together with v4 to get DSI working.

Maybe that helps,
-michael

[1] https://lore.kernel.org/all/20250402-cdns-dsi-impro-v2-3-4a093eaa5e27@ideasonboard.com/
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