[PATCH v8 11/15] drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer
Jessica Zhang
quic_jesszhan at quicinc.com
Tue Mar 4 21:56:11 UTC 2025
On 3/3/2025 7:14 AM, Jun Nie wrote:
> The stage contains configuration for a mixer pair. Currently the plane
> supports just one stage and 2 pipes. Quad-pipe support will require
> handling 2 stages and 4 pipes at the same time. In preparation for that
> add a separate define, PIPES_PER_PLANE, to denote number of pipes that
> can be used by the plane.
Hi Jun,
Sorry for missing this in the last revision, but it seems to me that the
looping of the pipes in `_dpu_debugfs_status_show()` should also be
using PIPES_PER_PLANE.
Thanks,
Jessica Zhang
>
> Signed-off-by: Jun Nie <jun.nie at linaro.org>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 16 ++++++++--------
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 ++--
> 4 files changed, 13 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index 193818b02197d0737c86de7765d98732fa914e8e..81474823e6799132db71c9712046d359e3535d90 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -463,7 +463,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
> if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
> bg_alpha_enable = true;
>
> - for (i = 0; i < PIPES_PER_STAGE; i++) {
> + for (i = 0; i < PIPES_PER_PLANE; i++) {
> if (!pstate->pipe[i].sspp)
> continue;
> set_bit(pstate->pipe[i].sspp->idx, fetch_active);
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index ba7bb05efe9b8cac01a908e53121117e130f91ec..74bf3ab9d6cfb8152b32d89a6c66e4d92d5cee1d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -34,7 +34,9 @@
> #define DPU_MAX_PLANES 4
> #endif
>
> +#define STAGES_PER_PLANE 1
> #define PIPES_PER_STAGE 2
> +#define PIPES_PER_PLANE (PIPES_PER_STAGE * STAGES_PER_PLANE)
> #ifndef DPU_MAX_DE_CURVES
> #define DPU_MAX_DE_CURVES 3
> #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> index ef44af5ab681c8f526333fa92531a2225983aa09..1095727d1d9f17407f2b063039bf2efd8733ec70 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
> @@ -633,7 +633,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdpu,
> return;
>
> /* update sspp */
> - for (i = 0; i < PIPES_PER_STAGE; i++) {
> + for (i = 0; i < PIPES_PER_PLANE; i++) {
> if (!pstate->pipe[i].sspp)
> continue;
> _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i],
> @@ -1078,7 +1078,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_plane *plane,
> * resources are freed by dpu_crtc_assign_plane_resources(),
> * but clean them here.
> */
> - for (i = 0; i < PIPES_PER_STAGE; i++)
> + for (i = 0; i < PIPES_PER_PLANE; i++)
> pstate->pipe[i].sspp = NULL;
>
> return 0;
> @@ -1129,7 +1129,7 @@ static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc,
> pipe_cfg = &pstate->pipe_cfg[0];
> r_pipe_cfg = &pstate->pipe_cfg[1];
>
> - for (i = 0; i < PIPES_PER_STAGE; i++)
> + for (i = 0; i < PIPES_PER_PLANE; i++)
> pstate->pipe[i].sspp = NULL;
>
> if (!plane_state->fb)
> @@ -1241,7 +1241,7 @@ void dpu_plane_flush(struct drm_plane *plane)
> /* force 100% alpha */
> _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF);
> else {
> - for (i = 0; i < PIPES_PER_STAGE; i++)
> + for (i = 0; i < PIPES_PER_PLANE; i++)
> dpu_plane_flush_csc(pdpu, &pstate->pipe[i]);
> }
>
> @@ -1364,7 +1364,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane,
> &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt));
>
> /* move the assignment here, to ease handling to another pairs later */
> - for (i = 0; i < PIPES_PER_STAGE; i++) {
> + for (i = 0; i < PIPES_PER_PLANE; i++) {
> if (!pstate->pipe[i].sspp)
> continue;
> dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i],
> @@ -1378,7 +1378,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane,
>
> pstate->plane_fetch_bw = 0;
> pstate->plane_clk = 0;
> - for (i = 0; i < PIPES_PER_STAGE; i++) {
> + for (i = 0; i < PIPES_PER_PLANE; i++) {
> if (!pstate->pipe[i].sspp)
> continue;
> pstate->plane_fetch_bw += _dpu_plane_calc_bw(pdpu->catalog, fmt,
> @@ -1397,7 +1397,7 @@ static void _dpu_plane_atomic_disable(struct drm_plane *plane)
> struct dpu_sw_pipe *pipe;
> int i;
>
> - for (i = 0; i < PIPES_PER_STAGE; i += 1) {
> + for (i = 0; i < PIPES_PER_PLANE; i += 1) {
> pipe = &pstate->pipe[i];
> if (!pipe->sspp)
> continue;
> @@ -1519,7 +1519,7 @@ static void dpu_plane_atomic_print_state(struct drm_printer *p,
>
> drm_printf(p, "\tstage=%d\n", pstate->stage);
>
> - for (i = 0; i < PIPES_PER_STAGE; i++) {
> + for (i = 0; i < PIPES_PER_PLANE; i++) {
> pipe = &pstate->pipe[i];
> if (!pipe->sspp)
> continue;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> index 052fd046e8463855b16b30389c2efc67c0c15281..18ff5ec2603ed63ce45f530ced3407d3b70c737b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
> @@ -33,8 +33,8 @@
> struct dpu_plane_state {
> struct drm_plane_state base;
> struct msm_gem_address_space *aspace;
> - struct dpu_sw_pipe pipe[PIPES_PER_STAGE];
> - struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE];
> + struct dpu_sw_pipe pipe[PIPES_PER_PLANE];
> + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_PLANE];
> enum dpu_stage stage;
> bool needs_qos_remap;
> bool pending;
>
> --
> 2.34.1
>
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