[PATCH v5 1/6] drm/v3d: Associate a V3D tech revision to all supported devices
Stefan Wahren
wahrenst at gmx.net
Sun Mar 16 16:51:22 UTC 2025
Hi Maíra,
Am 16.03.25 um 15:15 schrieb Maíra Canal:
> The V3D driver currently determines the GPU tech version (33, 41...)
> by reading a register. This approach has worked so far since this
> information wasn’t needed before powering on the GPU.
>
> V3D 7.1 introduces new registers that must be written to power on the
> GPU, requiring us to know the V3D version beforehand. To address this,
> associate each supported SoC with the corresponding VideoCore GPU version
> as part of the device data.
>
> To prevent possible mistakes, add an assertion to verify that the version
> specified in the device data matches the one reported by the hardware.
> If there is a mismatch, the kernel will trigger a warning.
>
> Reviewed-by: Iago Toral Quiroga <itoral at igalia.com>
> Signed-off-by: Maíra Canal <mcanal at igalia.com>
> ---
> drivers/gpu/drm/v3d/v3d_debugfs.c | 126 +++++++++++++++++++-------------------
> drivers/gpu/drm/v3d/v3d_drv.c | 22 +++++--
> drivers/gpu/drm/v3d/v3d_drv.h | 11 +++-
> drivers/gpu/drm/v3d/v3d_gem.c | 10 +--
> drivers/gpu/drm/v3d/v3d_irq.c | 6 +-
> drivers/gpu/drm/v3d/v3d_perfmon.c | 4 +-
> drivers/gpu/drm/v3d/v3d_sched.c | 6 +-
> 7 files changed, 101 insertions(+), 84 deletions(-)
>
> diff --git a/drivers/gpu/drm/v3d/v3d_debugfs.c b/drivers/gpu/drm/v3d/v3d_debugfs.c
> index 76816f2551c10026a775e4331ad7eb2f008cfb0a..7e789e181af0ac138044f194a29555c30ab01836 100644
> --- a/drivers/gpu/drm/v3d/v3d_debugfs.c
> +++ b/drivers/gpu/drm/v3d/v3d_debugfs.c
> @@ -21,74 +21,74 @@ struct v3d_reg_def {
> };
>
> static const struct v3d_reg_def v3d_hub_reg_defs[] = {
> - REGDEF(33, 42, V3D_HUB_AXICFG),
> - REGDEF(33, 71, V3D_HUB_UIFCFG),
> - REGDEF(33, 71, V3D_HUB_IDENT0),
> - REGDEF(33, 71, V3D_HUB_IDENT1),
> - REGDEF(33, 71, V3D_HUB_IDENT2),
> - REGDEF(33, 71, V3D_HUB_IDENT3),
> - REGDEF(33, 71, V3D_HUB_INT_STS),
> - REGDEF(33, 71, V3D_HUB_INT_MSK_STS),
> -
> - REGDEF(33, 71, V3D_MMU_CTL),
> - REGDEF(33, 71, V3D_MMU_VIO_ADDR),
> - REGDEF(33, 71, V3D_MMU_VIO_ID),
> - REGDEF(33, 71, V3D_MMU_DEBUG_INFO),
> -
> - REGDEF(71, 71, V3D_GMP_STATUS(71)),
> - REGDEF(71, 71, V3D_GMP_CFG(71)),
> - REGDEF(71, 71, V3D_GMP_VIO_ADDR(71)),
> + REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_HUB_AXICFG),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_UIFCFG),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT0),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT1),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT2),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT3),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_STS),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_MSK_STS),
> +
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_CTL),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ADDR),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ID),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_DEBUG_INFO),
> +
> + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_STATUS(71)),
> + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_CFG(71)),
> + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_VIO_ADDR(71)),
> };
>
> static const struct v3d_reg_def v3d_gca_reg_defs[] = {
> - REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN),
> - REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN_ACK),
> + REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN),
> + REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN_ACK),
> };
>
> static const struct v3d_reg_def v3d_core_reg_defs[] = {
> - REGDEF(33, 71, V3D_CTL_IDENT0),
> - REGDEF(33, 71, V3D_CTL_IDENT1),
> - REGDEF(33, 71, V3D_CTL_IDENT2),
> - REGDEF(33, 71, V3D_CTL_MISCCFG),
> - REGDEF(33, 71, V3D_CTL_INT_STS),
> - REGDEF(33, 71, V3D_CTL_INT_MSK_STS),
> - REGDEF(33, 71, V3D_CLE_CT0CS),
> - REGDEF(33, 71, V3D_CLE_CT0CA),
> - REGDEF(33, 71, V3D_CLE_CT0EA),
> - REGDEF(33, 71, V3D_CLE_CT1CS),
> - REGDEF(33, 71, V3D_CLE_CT1CA),
> - REGDEF(33, 71, V3D_CLE_CT1EA),
> -
> - REGDEF(33, 71, V3D_PTB_BPCA),
> - REGDEF(33, 71, V3D_PTB_BPCS),
> -
> - REGDEF(33, 42, V3D_GMP_STATUS(33)),
> - REGDEF(33, 42, V3D_GMP_CFG(33)),
> - REGDEF(33, 42, V3D_GMP_VIO_ADDR(33)),
> -
> - REGDEF(33, 71, V3D_ERR_FDBGO),
> - REGDEF(33, 71, V3D_ERR_FDBGB),
> - REGDEF(33, 71, V3D_ERR_FDBGS),
> - REGDEF(33, 71, V3D_ERR_STAT),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT0),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT1),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT2),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_MISCCFG),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_STS),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_MSK_STS),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CS),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CA),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0EA),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CS),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CA),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1EA),
> +
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCA),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCS),
> +
> + REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_STATUS(33)),
> + REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_CFG(33)),
> + REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_VIO_ADDR(33)),
> +
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGO),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGB),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGS),
> + REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_STAT),
> };
>
> static const struct v3d_reg_def v3d_csd_reg_defs[] = {
> - REGDEF(41, 71, V3D_CSD_STATUS),
> - REGDEF(41, 42, V3D_CSD_CURRENT_CFG0(41)),
> - REGDEF(41, 42, V3D_CSD_CURRENT_CFG1(41)),
> - REGDEF(41, 42, V3D_CSD_CURRENT_CFG2(41)),
> - REGDEF(41, 42, V3D_CSD_CURRENT_CFG3(41)),
> - REGDEF(41, 42, V3D_CSD_CURRENT_CFG4(41)),
> - REGDEF(41, 42, V3D_CSD_CURRENT_CFG5(41)),
> - REGDEF(41, 42, V3D_CSD_CURRENT_CFG6(41)),
> - REGDEF(71, 71, V3D_CSD_CURRENT_CFG0(71)),
> - REGDEF(71, 71, V3D_CSD_CURRENT_CFG1(71)),
> - REGDEF(71, 71, V3D_CSD_CURRENT_CFG2(71)),
> - REGDEF(71, 71, V3D_CSD_CURRENT_CFG3(71)),
> - REGDEF(71, 71, V3D_CSD_CURRENT_CFG4(71)),
> - REGDEF(71, 71, V3D_CSD_CURRENT_CFG5(71)),
> - REGDEF(71, 71, V3D_CSD_CURRENT_CFG6(71)),
> - REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG7),
> + REGDEF(V3D_GEN_41, V3D_GEN_71, V3D_CSD_STATUS),
> + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG0(41)),
> + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG1(41)),
> + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG2(41)),
> + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG3(41)),
> + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG4(41)),
> + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG5(41)),
> + REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG6(41)),
> + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG0(71)),
> + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG1(71)),
> + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG2(71)),
> + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG3(71)),
> + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG4(71)),
> + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG5(71)),
> + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG6(71)),
> + REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG7),
> };
>
> static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
> @@ -164,7 +164,7 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
> str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
> seq_printf(m, "TFU: %s\n",
> str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
> - if (v3d->ver <= 42) {
> + if (v3d->ver <= V3D_GEN_42) {
> seq_printf(m, "TSY: %s\n",
> str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
> }
> @@ -196,11 +196,11 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
> seq_printf(m, " QPUs: %d\n", nslc * qups);
> seq_printf(m, " Semaphores: %d\n",
> V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
> - if (v3d->ver <= 42) {
> + if (v3d->ver <= V3D_GEN_42) {
> seq_printf(m, " BCG int: %d\n",
> (ident2 & V3D_IDENT2_BCG_INT) != 0);
> }
> - if (v3d->ver < 40) {
> + if (v3d->ver < V3D_GEN_41) {
I had expected that such a behavior change was at least mentioned in the
commit log.
Except of this, look good to me.
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