[PATCH v4 01/15] clk: renesas: rzv2h-cpg: Add support for DSI clocks

[ALOK TIWARI]

On 01-05-2025 02:10, Prabhakar wrote:
> From: Lad Prabhakar<prabhakar.mahadev-lad.rj at bp.renesas.com>
> 
> Add support for PLLDSI and PLLDSI divider clocks.
> 
> Introduce the `renesas-rzv2h-dsi.h` header to centralize and share
> PLLDSI-related data structures, limits, and algorithms between the RZ/V2H
> CPG and DSI drivers.
> 
> The DSI PLL is functionally similar to the CPG's PLLDSI, but has slightly
> different parameter limits and omits the programmable divider present in
> CPG. To ensure precise frequency calculations-especially for milliHz-level
> accuracy needed by the DSI driver-the shared algorithm allows both drivers
> to compute PLL parameters consistently using the same logic and input
> clock.
> 
> Co-developed-by: Fabrizio Castro<fabrizio.castro.jz at renesas.com>
> Signed-off-by: Fabrizio Castro<fabrizio.castro.jz at renesas.com>
> Signed-off-by: Lad Prabhakar<prabhakar.mahadev-lad.rj at bp.renesas.com>


Acked-by: Alok Tiwari <alok.a.tiwari at oracle.com>

Thanks,
Alok