[PATCH v2 7/7] gpu: nova-core: Clarify falcon code

[Zhi Wang]

On Sat,  3 May 2025 00:07:59 -0400
Joel Fernandes <joelagnelf at nvidia.com> wrote:

> Add documentation strings, comments and AES mode for completeness
> to the Falcon signatures.
> 
> Signed-off-by: Joel Fernandes <joelagnelf at nvidia.com>
> ---
>  drivers/gpu/nova-core/falcon.rs | 25 +++++++++++++++++++------
>  1 file changed, 19 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/nova-core/falcon.rs
> b/drivers/gpu/nova-core/falcon.rs index e9ee0c83dfc5..003db40d3303
> 100644 --- a/drivers/gpu/nova-core/falcon.rs
> +++ b/drivers/gpu/nova-core/falcon.rs
> @@ -89,13 +89,19 @@ fn try_from(value: u8) -> Result<Self> {
>  /// register.
>  #[repr(u8)]
>  #[derive(Debug, Default, Copy, Clone)]
> +/// Security mode of the Falcon microprocessor.
> +/// See falcon.rst for more details.
>  pub(crate) enum FalconSecurityModel {
>      /// Non-Secure: runs unsigned code without privileges.
>      #[default]
>      None = 0,
> -    /// Low-secure: runs unsigned code with some privileges. Can
> only be entered from `Heavy` mode.
> +    /// Light-Secured (LS): runs signed code with some privileges
> +    /// Its signature can only be verified and entered from `Heavy`
> mode.
> +    /// Also known as Privilege Level 2 or PL2.
>      Light = 2,
> -    /// High-Secure: runs signed code with full privileges.
> +    /// Heavy-Secured: runs signed code with full privileges.
> +    /// Its signature can only be verified by the Falcon Boot ROM
> (BROM).
> +    /// Also known as Privilege Level 3 or PL3.
>      Heavy = 3,
>  }
>  
> @@ -117,10 +123,13 @@ fn try_from(value: u8) ->
> core::result::Result<Self, Self::Error> { }
>  
>  /// Signing algorithm for a given firmware, used in the
> [`crate::regs::NV_PFALCON2_FALCON_MOD_SEL`] -/// register.
> +/// register. It is passed to the Falcon Boot ROM (BROM) as a
> parameter. #[repr(u8)]
>  #[derive(Debug, Default, Copy, Clone, PartialEq, Eq)]
>  pub(crate) enum FalconModSelAlgo {
> +    /// AES.
> +    #[expect(dead_code)]
> +    Aes = 0,
>      /// RSA3K.
>      #[default]
>      Rsa3k = 1,
> @@ -184,15 +193,19 @@ pub(crate) enum FalconMem {
>      Dmem,
>  }
>  
> -/// Target/source of a DMA transfer to/from falcon memory.
> +/// FBIF (Framebuffer Interface) aperture type. Used to determine
> +/// the memory type of the external memory access for a DMA memory
> +/// transfer (by the Falcon's FramebufferDMA (FBDMA) engine located
                 Should be Framebuffer DMA?^ So that it will be aligned
with PATCH 6. 
> +/// inside the falcon). See falcon.rst for more details.
>  #[derive(Debug, Clone, Default)]
>  pub(crate) enum FalconFbifTarget {
>      /// VRAM.
>      #[default]
> +    /// Local Framebuffer (GPU's VRAM memory)
>      LocalFb = 0,
> -    /// Coherent system memory.
> +    /// Coherent system memory (System DRAM).
>      CoherentSysmem = 1,
> -    /// Non-coherent system memory.
> +    /// Non-coherent system memory (System DRAM).
>      NoncoherentSysmem = 2,
>  }
>