[PATCH v9 10/14] drm/msm/dpu: Use dedicated WB number definition

[Jessica Zhang]

On 5/6/2025 8:47 AM, Jun Nie wrote:
> Currently MAX_CHANNELS_PER_ENC is defined as 2, because 2 channels are
> supported at most in one encoder. The case of 4 channels per encoder is
> to be added. To avoid breaking current WB usage case, use dedicated WB
> definition before 4 WB usage case is supported in future.
> 
> Signed-off-by: Jun Nie <jun.nie at linaro.org>

Reviewed-by: Jessica Zhang <quic_jesszhan at quicinc.com>

> ---
>   drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 3e4ff345bd6d9c0e2a08274874fac40690409cf0..a125a477404fdafee6495f6d3778160f14a01a96 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -56,6 +56,7 @@
>   	(MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
>   
>   #define MAX_CHANNELS_PER_ENC 2
> +#define MAX_CWB_PER_ENC 2
>   
>   #define IDLE_SHORT_TIMEOUT	1
>   
> @@ -182,7 +183,7 @@ struct dpu_encoder_virt {
>   	struct dpu_encoder_phys *cur_master;
>   	struct dpu_encoder_phys *cur_slave;
>   	struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> -	struct dpu_hw_cwb *hw_cwb[MAX_CHANNELS_PER_ENC];
> +	struct dpu_hw_cwb *hw_cwb[MAX_CWB_PER_ENC];
>   	struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
>   
>   	unsigned int dsc_mask;
> @@ -2372,7 +2373,7 @@ void dpu_encoder_helper_phys_setup_cwb(struct dpu_encoder_phys *phys_enc,
>   	 */
>   	cwb_cfg.input = INPUT_MODE_LM_OUT;
>   
> -	for (int i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> +	for (int i = 0; i < MAX_CWB_PER_ENC; i++) {
>   		hw_cwb = dpu_enc->hw_cwb[i];
>   		if (!hw_cwb)
>   			continue;
>