[PATCH RFT v2 12/15] drm/msm/a6xx: Drop cfg->ubwc_swizzle override

[Dmitry Baryshkov]

On Wed, May 14, 2025 at 05:10:32PM +0200, Konrad Dybcio wrote:
> From: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
> 
> On A663 (SA8775P) the value matches exactly.
> 
> On A610, the value matches on SM6115, but is different on SM6125. That
> turns out not to be a problem, as the bits that differ aren't even
> interpreted.

We also don't set swizzle for a lot of UBWC 1.0 targets (as MDSS wasn't
programming those). Should we fix all of them to use 6 by default? Or 7?

> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
> ---
>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 ++-------
>  1 file changed, 2 insertions(+), 7 deletions(-)
> 

-- 
With best wishes
Dmitry