[PATCH RFT v2 10/15] drm/msm/a6xx: Simplify min_acc_len calculation

[Konrad Dybcio]

On 5/14/25 9:19 PM, Dmitry Baryshkov wrote:
> On Wed, May 14, 2025 at 05:10:30PM +0200, Konrad Dybcio wrote:
>> From: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
>>
>> It's only necessary for some lower end parts.
>> Also rename it to min_acc_len_64b to denote that if set, the minimum
>> access length is 64 bits, 32b otherwise.
>>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio at oss.qualcomm.com>
>> ---
>>  drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 15 ++++++---------
>>  1 file changed, 6 insertions(+), 9 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> index 5ee5f8dc90fe0d1647ce07b7dbcadc6ca2ecd416..fdc843c47c075a92ec8305217c355e4ccee876dc 100644
>> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
>> @@ -592,14 +592,12 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
>>  	if (IS_ERR(gpu->common_ubwc_cfg))
>>  		return -EINVAL;
>>  
>> -	gpu->ubwc_config.min_acc_len = 0;
>>  	gpu->ubwc_config.ubwc_swizzle = 0x6;
>>  	gpu->ubwc_config.macrotile_mode = 0;
>>  	gpu->ubwc_config.highest_bank_bit = 15;
> 
> It occurred to me that here (and in some previous patches) you stopped
> setting the field, but you didn't drop it from adreno_gpu.ubwc_config.
> Would you mind updating the patches in this way?
> 
> With that fixed:
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov at oss.qualcomm.com>

I mean.. I could.. but I delete the whole thing couple patches later

Konrad