[PATCH v4 08/30] drm/msm/dpu: get rid of DPU_CTL_HAS_LAYER_EXT4
neil.armstrong at linaro.org
neil.armstrong at linaro.org
Tue May 20 07:58:09 UTC 2025
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>
> Continue migration to the MDSS-revision based checks and replace
> DPU_CTL_HAS_LAYER_EXT4 feature bit with the core_major_ver >= 9 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> Reviewed-by: Abhinav Kumar <quic_abhinavk at quicinc.com>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 12 ++++++------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 --
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 5 ++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 ++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 2 +-
> 9 files changed, 33 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index b14d0d6886f019c8fa06047baf734e38696f14ce..52ad7e2af0148c9ea81a2c95b270be7058fbaec1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sm8650_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x1000,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 4c5785332b5240109af36a1256d4ea29c348bced..83f73c7cdcc3a280285fa32230796fac57167ed6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sm8550_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index 960c68f33074e0cec0f33aa7d4f8f3b4cc69bac5..b21aab274703ac1f38698bee82d5d28b0fb6a0d0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -31,32 +31,32 @@ static const struct dpu_ctl_cfg sar2130p_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index 85dcf577b844995fe11322ec506885bc4a85e33c..d7e5f4dd3bccab125b0a42f67eddf194359dc761 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -30,32 +30,32 @@ static const struct dpu_ctl_cfg x1e80100_ctl[] = {
> {
> .name = "ctl_0", .id = CTL_0,
> .base = 0x15000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
> }, {
> .name = "ctl_1", .id = CTL_1,
> .base = 0x16000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
> }, {
> .name = "ctl_2", .id = CTL_2,
> .base = 0x17000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
> }, {
> .name = "ctl_3", .id = CTL_3,
> .base = 0x18000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
> }, {
> .name = "ctl_4", .id = CTL_4,
> .base = 0x19000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
> }, {
> .name = "ctl_5", .id = CTL_5,
> .base = 0x1a000, .len = 0x290,
> - .features = CTL_SM8550_MASK,
> + .features = CTL_SC7280_MASK,
> .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
> },
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 00e6f3e56ed1f9af581bad9845971fad315ef83c..a162c4f9ebd79d3ba16b50117ee7462afdbbf3d4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -110,9 +110,6 @@
> BIT(DPU_CTL_VM_CFG) | \
> BIT(DPU_CTL_DSPP_SUB_BLOCK_FLUSH))
>
> -#define CTL_SM8550_MASK \
> - (CTL_SC7280_MASK | BIT(DPU_CTL_HAS_LAYER_EXT4))
> -
> #define INTF_SC7180_MASK \
> (BIT(DPU_INTF_INPUT_CTRL) | \
> BIT(DPU_INTF_STATUS_SUPPORTED) | \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 01dd6e65f777f3b92f41e2ccb08f279650d50425..3d6c2db395b65b89845cb7281195ca5ca16c22e6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -134,7 +134,6 @@ enum {
> * @DPU_CTL_SPLIT_DISPLAY: CTL supports video mode split display
> * @DPU_CTL_FETCH_ACTIVE: Active CTL for fetch HW (SSPPs)
> * @DPU_CTL_VM_CFG: CTL config to support multiple VMs
> - * @DPU_CTL_HAS_LAYER_EXT4: CTL has the CTL_LAYER_EXT4 register
> * @DPU_CTL_DSPP_BLOCK_FLUSH: CTL config to support dspp sub-block flush
> * @DPU_CTL_MAX
> */
> @@ -143,7 +142,6 @@ enum {
> DPU_CTL_ACTIVE_CFG,
> DPU_CTL_FETCH_ACTIVE,
> DPU_CTL_VM_CFG,
> - DPU_CTL_HAS_LAYER_EXT4,
> DPU_CTL_DSPP_SUB_BLOCK_FLUSH,
> DPU_CTL_MAX
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index d58a0f1e8edb524ff3f21ff8c96688dd2ae49541..58bdd4d33b37d83f30931f09fdf80bef41e1f0fe 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -555,7 +555,7 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx,
> DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg[1]);
> DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg[2]);
> DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg[3]);
> - if ((test_bit(DPU_CTL_HAS_LAYER_EXT4, &ctx->caps->features)))
> + if (ctx->mdss_ver->core_major_ver >= 9)
> DPU_REG_WRITE(c, CTL_LAYER_EXT4(lm), mixercfg[4]);
> }
>
> @@ -743,12 +743,14 @@ static void dpu_hw_ctl_set_active_fetch_pipes(struct dpu_hw_ctl *ctx,
> * @dev: Corresponding device for devres management
> * @cfg: ctl_path catalog entry for which driver object is required
> * @addr: mapped register io address of MDP
> + * @mdss_ver: dpu core's major and minor versions
> * @mixer_count: Number of mixers in @mixer
> * @mixer: Pointer to an array of Layer Mixers defined in the catalog
> */
> struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
> const struct dpu_ctl_cfg *cfg,
> void __iomem *addr,
> + const struct dpu_mdss_version *mdss_ver,
> u32 mixer_count,
> const struct dpu_lm_cfg *mixer)
> {
> @@ -762,6 +764,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
> c->hw.log_mask = DPU_DBG_MASK_CTL;
>
> c->caps = cfg;
> + c->mdss_ver = mdss_ver;
>
> if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) {
> c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index feb09590bc8fc5c77c2c673fd888c28281a98b5a..9cd9959682c21cc1c6d8d14b8fb377deb33cc10d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -274,6 +274,7 @@ struct dpu_hw_ctl_ops {
> * @pending_cwb_flush_mask: pending CWB flush
> * @pending_dsc_flush_mask: pending DSC flush
> * @pending_cdm_flush_mask: pending CDM flush
> + * @mdss_ver: MDSS revision information
> * @ops: operation list
> */
> struct dpu_hw_ctl {
> @@ -295,6 +296,8 @@ struct dpu_hw_ctl {
> u32 pending_dsc_flush_mask;
> u32 pending_cdm_flush_mask;
>
> + const struct dpu_mdss_version *mdss_ver;
> +
> /* ops */
> struct dpu_hw_ctl_ops ops;
> };
> @@ -312,6 +315,7 @@ static inline struct dpu_hw_ctl *to_dpu_hw_ctl(struct dpu_hw_blk *hw)
> struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev,
> const struct dpu_ctl_cfg *cfg,
> void __iomem *addr,
> + const struct dpu_mdss_version *mdss_ver,
> u32 mixer_count,
> const struct dpu_lm_cfg *mixer);
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index 2e296f79cba1437470eeb30900a650f6f4e334b6..d728e275ac427f7849dad4f4a055c56840ca2d23 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -142,7 +142,7 @@ int dpu_rm_init(struct drm_device *dev,
> struct dpu_hw_ctl *hw;
> const struct dpu_ctl_cfg *ctl = &cat->ctl[i];
>
> - hw = dpu_hw_ctl_init(dev, ctl, mmio, cat->mixer_count, cat->mixer);
> + hw = dpu_hw_ctl_init(dev, ctl, mmio, cat->mdss_ver, cat->mixer_count, cat->mixer);
> if (IS_ERR(hw)) {
> rc = PTR_ERR(hw);
> DPU_ERROR("failed ctl object creation: err %d\n", rc);
>
Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
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