[PATCH v4 25/30] drm/msm/dpu: get rid of DPU_WB_INPUT_CTRL
neil.armstrong at linaro.org
neil.armstrong at linaro.org
Tue May 20 08:04:35 UTC 2025
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> Continue migration to the MDSS-revision based checks and replace
> DPU_WB_INPUT_CTRL feature bit with the core_major_ver >= 5 check.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 2 +-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 3 ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 2 +-
> 19 files changed, 17 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> index 013314b2e716a6d939393b77b0edc87170dba27b..56d3c38c87781edb438b277c77382848b679198f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
> @@ -318,7 +318,7 @@ static const struct dpu_wb_cfg sm8650_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .xin_id = 6,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index 5d3b864d28a86fb86fc4576210c9418604afd844..ae1b2ed96e9f10a6e7a710fc8bb4e40dec665cf9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -275,7 +275,7 @@ static const struct dpu_wb_cfg sm8150_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index a6e9dfc583f283d752545b3f700c3d509e2a2965..fc80406759cd52f0d633927c8ba876feaff48e07 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -281,7 +281,7 @@ static const struct dpu_wb_cfg sc8180x_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> index fe9c9301e3d9d2d3a0a34ab9aed0f307d08c34ca..a56c288ac10cd3dfe8d49a6e476b9fff062f8003 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h
> @@ -241,7 +241,7 @@ static const struct dpu_wb_cfg sm7150_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> index 8fb926bff36d32fb4ce1036cb69513599dc7b6b7..a065f102ce592311376f1186add7a47dca7fd84f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> @@ -154,7 +154,7 @@ static const struct dpu_wb_cfg sm6150_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> index 5c2c8c5f812347970c534769d72f9699e6e7049a..2950245e7b3f5e38f3f501a7314bb97c66d05982 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> @@ -133,7 +133,7 @@ static const struct dpu_wb_cfg sm6125_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index 9ceff398fd6f554085440f509b6f8398b4fbf304..7b8b7a1c2d767eafca7e7440098bb28e2e108902 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -312,7 +312,7 @@ static const struct dpu_wb_cfg sm8250_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index f6a0f1a39dcc3c9e82c07889d71905434274cdf9..c990ba3b5db02d65934179d5ad42bd740f6944b2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -148,7 +148,7 @@ static const struct dpu_wb_cfg sc7180_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> index a46e9e3ff565ba5ef233af76f1c6cebb1d0c318a..093d16bdc450af348da1775ff017d982236b11b0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
> @@ -142,7 +142,7 @@ static const struct dpu_wb_cfg sm6350_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index b4d41e2644349bdbdbdacbe1e9b3748f90df4f3b..85aae40c210f3aa1b29bf0b5ea81ee1f551a6ef6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -285,7 +285,7 @@ static const struct dpu_wb_cfg sm8350_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 5d88f0261d8320a78f8d64c9bb68b938f83160a0..8f978b9c345202d3ea1a7781e4ef2763b46c6f6e 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -159,7 +159,7 @@ static const struct dpu_wb_cfg sc7280_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 3c0728a4b37ea6af25ab64315cfe63ba6f8d2774..b09a6af4c474aa9301c0ef6bc0ce71ba42cce3a2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -298,7 +298,7 @@ static const struct dpu_wb_cfg sm8450_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> index b8a1646395916fde04b9750cf548edca5729d9c2..0f7b4a224e4c971f482c3778c92e8c170b44223f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.h
> @@ -305,7 +305,7 @@ static const struct dpu_wb_cfg sa8775p_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .clk_ctrl = DPU_CLK_CTRL_WB2,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index ef22a9adf43ddc9d15be5f1359ea5f6690e9f27c..465b6460f8754df18bbcf4baac2f8a3ebdea3324 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -294,7 +294,7 @@ static const struct dpu_wb_cfg sm8550_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .xin_id = 6,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> index 2e7d4403835353927bc85a5acd3e6c5967cac455..6caa7d40f368802793c8690544c1c82b49a617cd 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_1_sar2130p.h
> @@ -294,7 +294,7 @@ static const struct dpu_wb_cfg sar2130p_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .xin_id = 6,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> index ac95d46b3ecf2d95ec0d516a79567fe9c204b5f6..7243eebb85f36f2a8ae848f2c95d21b0bc3bebef 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h
> @@ -294,7 +294,7 @@ static const struct dpu_wb_cfg x1e80100_wb[] = {
> {
> .name = "wb_2", .id = WB_2,
> .base = 0x65000, .len = 0x2c8,
> - .features = WB_SM8250_MASK,
> + .features = WB_SDM845_MASK,
> .format_list = wb2_formats_rgb_yuv,
> .num_formats = ARRAY_SIZE(wb2_formats_rgb_yuv),
> .xin_id = 6,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index ad0460aa5b5ce5a373dab18c89e4159855da4d2b..6d7be74bafe326a1998a69ed9b3495c5acf6350f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -98,9 +98,6 @@
> BIT(DPU_WB_QOS_8LVL) | \
> BIT(DPU_WB_CDP))
>
> -#define WB_SM8250_MASK (WB_SDM845_MASK | \
> - BIT(DPU_WB_INPUT_CTRL))
> -
> #define DEFAULT_PIXEL_RAM_SIZE (50 * 1024)
> #define DEFAULT_DPU_LINE_WIDTH 2048
> #define DEFAULT_DPU_OUTPUT_LINE_WIDTH 2560
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 41906dadff5a8ef39b2e90f3e80bb699a5cf59b7..8c394e7d6496ca2d120c81c7776b4b979368be23 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -140,8 +140,6 @@ enum {
> * @DPU_WB_QOS, Writeback supports QoS control, danger/safe/creq
> * @DPU_WB_QOS_8LVL, Writeback supports 8-level QoS control
> * @DPU_WB_CDP Writeback supports client driven prefetch
> - * @DPU_WB_INPUT_CTRL Writeback supports from which pp block input pixel
> - * data arrives.
> * @DPU_WB_CROP CWB supports cropping
> * @DPU_WB_MAX maximum value
> */
> @@ -155,7 +153,6 @@ enum {
> DPU_WB_QOS,
> DPU_WB_QOS_8LVL,
> DPU_WB_CDP,
> - DPU_WB_INPUT_CTRL,
> DPU_WB_CROP,
> DPU_WB_MAX
> };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> index 4853e516c48733231de240b9c32ad51d4cf18f0d..478a091aeccfc7cf298798e1c119df56737e3dc4 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
> @@ -208,7 +208,7 @@ static void _setup_wb_ops(struct dpu_hw_wb_ops *ops,
> if (test_bit(DPU_WB_CDP, &features))
> ops->setup_cdp = dpu_hw_wb_setup_cdp;
>
> - if (test_bit(DPU_WB_INPUT_CTRL, &features))
> + if (mdss_rev->core_major_ver >= 5)
> ops->bind_pingpong_blk = dpu_hw_wb_bind_pingpong_blk;
>
> if (mdss_rev->core_major_ver >= 9)
>
Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
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