[PATCH v4 30/30] drm/msm/dpu: move features out of the DPU_HW_BLK_INFO
neil.armstrong at linaro.org
neil.armstrong at linaro.org
Tue May 20 08:05:47 UTC 2025
On 19/05/2025 18:04, Dmitry Baryshkov wrote:
> From: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
>
> As features bits are now unused by some of the hardware block
> configuration structures, remove the 'features' from the DPU_HW_BLK_INFO
> so that it doesn't get included into hw info structures by default and
> only include it when necessary.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov at oss.qualcomm.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 1 -
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 17 +++++++----------
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c | 5 ++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c | 5 ++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 4 ++--
> 6 files changed, 13 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> index a065f102ce592311376f1186add7a47dca7fd84f..26883f6b66b3e506d14eeb1c0bd64f556d19fef8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_3_sm6150.h
> @@ -20,7 +20,6 @@ static const struct dpu_caps sm6150_dpu_caps = {
> static const struct dpu_mdp_cfg sm6150_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x45c,
> - .features = 0,
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> index 2950245e7b3f5e38f3f501a7314bb97c66d05982..fbf50f279e6628cb0f92b0188e1fbdf156a899e2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
> @@ -22,7 +22,6 @@ static const struct dpu_caps sm6125_dpu_caps = {
> static const struct dpu_mdp_cfg sm6125_mdp = {
> .name = "top_0",
> .base = 0x0, .len = 0x45c,
> - .features = 0,
> .clk_ctrls = {
> [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
> [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index d51f6c5cdf62f3c00829167172ef6fd61f069986..47d82b83ac5378cb0001b3ea6605dc0f98aec5ef 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -154,14 +154,12 @@ enum {
> * @id: enum identifying this block
> * @base: register base offset to mdss
> * @len: length of hardware block
> - * @features bit mask identifying sub-blocks/features
> */
> #define DPU_HW_BLK_INFO \
> char name[DPU_HW_BLK_NAME_LEN]; \
> u32 id; \
> u32 base; \
> - u32 len; \
> - unsigned long features
> + u32 len
>
> /**
> * struct dpu_scaler_blk: Scaler information
> @@ -376,7 +374,6 @@ struct dpu_clk_ctrl_reg {
> /* struct dpu_mdp_cfg : MDP TOP-BLK instance info
> * @id: index identifying this block
> * @base: register base offset to mdss
> - * @features bit mask identifying sub-blocks/features
> * @clk_ctrls clock control register definition
> */
> struct dpu_mdp_cfg {
> @@ -392,6 +389,7 @@ struct dpu_mdp_cfg {
> */
> struct dpu_ctl_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> unsigned int intr_start;
> };
>
> @@ -407,6 +405,7 @@ struct dpu_ctl_cfg {
> */
> struct dpu_sspp_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> const struct dpu_sspp_sub_blks *sblk;
> u32 xin_id;
> enum dpu_clk_ctrl_type clk_ctrl;
> @@ -424,6 +423,7 @@ struct dpu_sspp_cfg {
> */
> struct dpu_lm_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> const struct dpu_lm_sub_blks *sblk;
> u32 pingpong;
> u32 dspp;
> @@ -434,7 +434,6 @@ struct dpu_lm_cfg {
> * struct dpu_dspp_cfg - information of DSPP blocks
> * @id enum identifying this block
> * @base register offset of this block
> - * @features bit mask identifying sub-blocks/features
> * supported by this block
> * @sblk sub-blocks information
> */
> @@ -447,7 +446,6 @@ struct dpu_dspp_cfg {
> * struct dpu_pingpong_cfg - information of PING-PONG blocks
> * @id enum identifying this block
> * @base register offset of this block
> - * @features bit mask identifying sub-blocks/features
> * @intr_done: index for PINGPONG done interrupt
> * @intr_rdptr: index for PINGPONG readpointer done interrupt
> * @sblk sub-blocks information
> @@ -464,8 +462,6 @@ struct dpu_pingpong_cfg {
> * struct dpu_merge_3d_cfg - information of DSPP blocks
> * @id enum identifying this block
> * @base register offset of this block
> - * @features bit mask identifying sub-blocks/features
> - * supported by this block
> * @sblk sub-blocks information
> */
> struct dpu_merge_3d_cfg {
> @@ -483,6 +479,7 @@ struct dpu_merge_3d_cfg {
> */
> struct dpu_dsc_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> const struct dpu_dsc_sub_blks *sblk;
> };
>
> @@ -490,7 +487,6 @@ struct dpu_dsc_cfg {
> * struct dpu_intf_cfg - information of timing engine blocks
> * @id enum identifying this block
> * @base register offset of this block
> - * @features bit mask identifying sub-blocks/features
> * @type: Interface type(DSI, DP, HDMI)
> * @controller_id: Controller Instance ID in case of multiple of intf type
> * @prog_fetch_lines_worst_case Worst case latency num lines needed to prefetch
> @@ -521,6 +517,7 @@ struct dpu_intf_cfg {
> */
> struct dpu_wb_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> u8 vbif_idx;
> u32 maxlinewidth;
> u32 xin_id;
> @@ -589,6 +586,7 @@ struct dpu_vbif_qos_tbl {
> */
> struct dpu_vbif_cfg {
> DPU_HW_BLK_INFO;
> + unsigned long features;
> u32 default_ot_rd_limit;
> u32 default_ot_wr_limit;
> u32 xin_halt_timeout;
> @@ -606,7 +604,6 @@ struct dpu_vbif_cfg {
> * @name string name for debug purposes
> * @id enum identifying this block
> * @base register offset of this block
> - * @features bit mask identifying sub-blocks/features
> */
> struct dpu_cdm_cfg {
> DPU_HW_BLK_INFO;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c
> index b9c433567262a954b7f02233f6670ee6a8476846..b3395e9c34a19363019ec0ccfb0c87943553b4c9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc_1_2.c
> @@ -360,8 +360,7 @@ static void dpu_hw_dsc_bind_pingpong_blk_1_2(struct dpu_hw_dsc *hw_dsc,
> DPU_REG_WRITE(hw, sblk->ctl.base + DSC_CTL, mux_cfg);
> }
>
> -static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops,
> - const unsigned long features)
> +static void _setup_dcs_ops_1_2(struct dpu_hw_dsc_ops *ops)
> {
> ops->dsc_disable = dpu_hw_dsc_disable_1_2;
> ops->dsc_config = dpu_hw_dsc_config_1_2;
> @@ -391,7 +390,7 @@ struct dpu_hw_dsc *dpu_hw_dsc_init_1_2(struct drm_device *dev,
>
> c->idx = cfg->id;
> c->caps = cfg;
> - _setup_dcs_ops_1_2(&c->ops, c->caps->features);
> + _setup_dcs_ops_1_2(&c->ops);
>
> return c;
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
> index 0b3325f9c8705999e1003e5c88872562e880229b..83b1dbecddd2b30402f47155fa2f9a148ead02c1 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_merge3d.c
> @@ -33,8 +33,7 @@ static void dpu_hw_merge_3d_setup_3d_mode(struct dpu_hw_merge_3d *merge_3d,
> }
> }
>
> -static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c,
> - unsigned long features)
> +static void _setup_merge_3d_ops(struct dpu_hw_merge_3d *c)
> {
> c->ops.setup_3d_mode = dpu_hw_merge_3d_setup_3d_mode;
> };
> @@ -62,7 +61,7 @@ struct dpu_hw_merge_3d *dpu_hw_merge_3d_init(struct drm_device *dev,
>
> c->idx = cfg->id;
> c->caps = cfg;
> - _setup_merge_3d_ops(c, c->caps->features);
> + _setup_merge_3d_ops(c);
>
> return c;
> }
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> index 5c811f0142d5e2a012d7e9b3a918818f22ec11cf..96dc10589bee6cf144eabaecf9f8ec5777431ac3 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
> @@ -264,7 +264,7 @@ static void dpu_hw_dp_phy_intf_sel(struct dpu_hw_mdp *mdp,
> }
>
> static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
> - unsigned long cap, const struct dpu_mdss_version *mdss_rev)
> + const struct dpu_mdss_version *mdss_rev)
> {
> ops->setup_split_pipe = dpu_hw_setup_split_pipe;
> ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
> @@ -313,7 +313,7 @@ struct dpu_hw_mdp *dpu_hw_mdptop_init(struct drm_device *dev,
> * Assign ops
> */
> mdp->caps = cfg;
> - _setup_mdp_ops(&mdp->ops, mdp->caps->features, mdss_rev);
> + _setup_mdp_ops(&mdp->ops, mdss_rev);
>
> return mdp;
> }
>
Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>
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