[PATCH v5 08/12] drm: renesas: rz-du: mipi_dsi: Use mHz for D-PHY frequency calculations

[Laurent Pinchart]

Hi Prabhakar,

Thank you for the patch.

On Mon, May 12, 2025 at 07:23:26PM +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> 
> Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
> precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
> high accuracy.

I have a hard time imagining the need for milliHz accuracy. Could you
please explain why that is needed on V2H ?

> These changes prepare the driver for upcoming RZ/V2H(P) SoC support.
> 
> Co-developed-by: Fabrizio Castro <fabrizio.castro.jz at renesas.com>
> Signed-off-by: Fabrizio Castro <fabrizio.castro.jz at renesas.com>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj at bp.renesas.com>
> Reviewed-by: Biju Das <biju.das.jz at bp.renesas.com>
> ---
> v4->v5:
> - Added Reviewed tag from Biju
> 
> v3->v4:
> - Used MILLI instead of KILO
> - Made use of mul_u32_u32() for multiplication
> 
> v2->v3:
> - Replaced `unsigned long long` with `u64`
> - Replaced *_mhz with *_millihz` in functions
> 
> v1->v2:
> - No changes
> ---
>  drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 13 ++++++++-----
>  1 file changed, 8 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> index 5fc607be0c46..f93519613662 100644
> --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c
> @@ -31,7 +31,7 @@
>  struct rzg2l_mipi_dsi;
>  
>  struct rzg2l_mipi_dsi_hw_info {
> -	int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, unsigned long hsfreq);
> +	int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz);
>  	void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
>  	u32 phy_reg_offset;
>  	u32 link_reg_offset;
> @@ -200,8 +200,9 @@ static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg)
>   */
>  
>  static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi,
> -				    unsigned long hsfreq)
> +				    u64 hsfreq_millihz)
>  {
> +	unsigned long hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);
>  	const struct rzg2l_mipi_dsi_timings *dphy_timings;
>  	unsigned int i;
>  	u32 dphyctrl0;
> @@ -274,6 +275,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
>  				  const struct drm_display_mode *mode)
>  {
>  	unsigned long hsfreq, vclk_rate;
> +	u64 hsfreq_millihz;
>  	unsigned int bpp;
>  	u32 txsetr;
>  	u32 clstptsetr;
> @@ -305,9 +307,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
>  	if (vclk_rate != mode->clock * MILLI)
>  		dev_info(dsi->dev, "Requested vclk rate %lu, actual %lu mismatch\n",
>  			 mode->clock * MILLI, vclk_rate);
> -	hsfreq = DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes);
> +	hsfreq_millihz = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(vclk_rate, bpp * MILLI), dsi->lanes);
>  
> -	ret = dsi->info->dphy_init(dsi, hsfreq);
> +	ret = dsi->info->dphy_init(dsi, hsfreq_millihz);
>  	if (ret < 0)
>  		goto err_phy;
>  
> @@ -315,6 +317,7 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi,
>  	txsetr = TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLEN;
>  	rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr);
>  
> +	hsfreq = DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI);
>  	/*
>  	 * Global timings characteristic depends on high speed Clock Frequency
>  	 * Currently MIPI DSI-IF just supports maximum FHD at 60 with:
> @@ -776,7 +779,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_device *pdev)
>  	 * mode->clock and format are not available. So initialize DPHY with
>  	 * timing parameters for 80Mbps.
>  	 */
> -	ret = dsi->info->dphy_init(dsi, 80000000);
> +	ret = dsi->info->dphy_init(dsi, 80000000ULL * MILLI);
>  	if (ret < 0)
>  		goto err_phy;
>  

-- 
Regards,

Laurent Pinchart