[PATCH 04/10] drm/i915/display: Add filter lut values

[Garg, Nemesa]

> -----Original Message-----
> From: Jani Nikula <jani.nikula at linux.intel.com>
> Sent: Monday, May 19, 2025 6:15 PM
> To: Garg, Nemesa <nemesa.garg at intel.com>; intel-gfx at lists.freedesktop.org;
> intel-xe at lists.freedesktop.org; dri-devel at lists.freedesktop.org
> Cc: Garg, Nemesa <nemesa.garg at intel.com>; Nautiyal, Ankit K
> <ankit.k.nautiyal at intel.com>
> Subject: Re: [PATCH 04/10] drm/i915/display: Add filter lut values
> 
> On Mon, 19 May 2025, Nemesa Garg <nemesa.garg at intel.com> wrote:
> > Add the register bits related to filter lut values.
> > These values are golden values and these value has to be loaded one
> > time while enabling the casf.
> >
> > v2: update commit message[Ankit]
> >
> > Signed-off-by: Nemesa Garg <nemesa.garg at intel.com>
> > Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal at intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_casf.c     | 22 +++++++++++++++++++
> >  drivers/gpu/drm/i915/display/intel_casf.h     |  3 +++
> >  .../gpu/drm/i915/display/intel_casf_regs.h    | 11 ++++++++++
> >  3 files changed, 36 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_casf.c
> > b/drivers/gpu/drm/i915/display/intel_casf.c
> > index 314d3fe19884..6dab67eb77ab 100644
> > --- a/drivers/gpu/drm/i915/display/intel_casf.c
> > +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> > @@ -30,6 +30,28 @@
> >   * original image.
> >   */
> >
> > +/* Default LUT values to be loaded one time. */ static const u16
> > +sharpness_lut[] = {
> > +	4095, 2047, 1364, 1022, 816, 678, 579,
> > +	504, 444, 397, 357, 323, 293, 268, 244, 224,
> > +	204, 187, 170, 154, 139, 125, 111, 98, 85,
> > +	73, 60, 48, 36, 24, 12, 0
> > +};
> > +
> > +void intel_filter_lut_load(struct intel_crtc *crtc,
> > +			   const struct intel_crtc_state *crtc_state)
> 
> Everything else in the file is prefixed intel_casf_, why is this called
> intel_filter_lut_load()?
> Will change to intel_casf_lut_load().
> > +{
> > +	struct intel_display *display = to_intel_display(crtc_state);
> > +	int i;
> > +
> > +	intel_de_write(display, SHRPLUT_INDEX(crtc->pipe),
> > +		       INDEX_AUTO_INCR | INDEX_VALUE(0));
> > +
> > +	for (i = 0; i < ARRAY_SIZE(sharpness_lut); i++)
> > +		intel_de_write(display, SHRPLUT_DATA(crtc->pipe),
> > +			       sharpness_lut[i]);
> > +}
> > +
> >  void intel_casf_update_strength(struct intel_crtc_state *crtc_state)
> > {
> >  	struct intel_display *display = to_intel_display(crtc_state); diff
> > --git a/drivers/gpu/drm/i915/display/intel_casf.h
> > b/drivers/gpu/drm/i915/display/intel_casf.h
> > index 83523fe66c48..80642809c08b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_casf.h
> > +++ b/drivers/gpu/drm/i915/display/intel_casf.h
> > @@ -9,9 +9,12 @@
> >  #include <linux/types.h>
> >
> >  struct intel_crtc_state;
> > +struct intel_crtc;
> >
> >  int intel_casf_compute_config(struct intel_crtc_state *crtc_state);
> > void intel_casf_update_strength(struct intel_crtc_state
> > *new_crtc_state);  void intel_casf_sharpness_get_config(struct
> > intel_crtc_state *crtc_state);
> > +void intel_filter_lut_load(struct intel_crtc *crtc,
> > +			   const struct intel_crtc_state *crtc_state);
> >
> >  #endif /* __INTEL_CASF_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_casf_regs.h
> > b/drivers/gpu/drm/i915/display/intel_casf_regs.h
> > index c24ba281ae37..b96950a48335 100644
> > --- a/drivers/gpu/drm/i915/display/intel_casf_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_casf_regs.h
> > @@ -19,4 +19,15 @@
> >  #define   SHARPNESS_FILTER_SIZE_5X5
> REG_FIELD_PREP(FILTER_SIZE_MASK, 1)
> >  #define   SHARPNESS_FILTER_SIZE_7X7
> REG_FIELD_PREP(FILTER_SIZE_MASK, 2)
> >
> > +#define _SHRPLUT_DATA_A                        0x682B8
> > +#define _SHRPLUT_DATA_B                        0x68AB8
> > +#define SHRPLUT_DATA(pipe)             _MMIO_PIPE(pipe,
> _SHRPLUT_DATA_A, _SHRPLUT_DATA_B)
> > +
> > +#define _SHRPLUT_INDEX_A               0x682B4
> > +#define _SHRPLUT_INDEX_B               0x68AB4
> > +#define SHRPLUT_INDEX(pipe)            _MMIO_PIPE(pipe,
> _SHRPLUT_INDEX_A, _SHRPLUT_INDEX_B)
> > +#define   INDEX_AUTO_INCR              REG_BIT(10)
> > +#define   INDEX_VALUE_MASK             REG_GENMASK(4, 0)
> > +#define   INDEX_VALUE(x)               REG_FIELD_PREP(INDEX_VALUE_MASK,
> (x))
> > +
> >  #endif /* __INTEL_CASF_REGS__ */
> 
> --
> Jani Nikula, Intel