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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - 144Hz graphic glitches and bad refresh rate"
href="https://bugs.freedesktop.org/show_bug.cgi?id=93826#c19">Comment # 19</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - 144Hz graphic glitches and bad refresh rate"
href="https://bugs.freedesktop.org/show_bug.cgi?id=93826">bug 93826</a>
from <span class="vcard"><a class="email" href="mailto:alexdeucher@gmail.com" title="Alex Deucher <alexdeucher@gmail.com>"> <span class="fn">Alex Deucher</span></a>
</span></b>
<pre>(In reply to Damien from <a href="show_bug.cgi?id=93826#c18">comment #18</a>)
<span class="quote">> Alex thank you for your return.
>
> Since my monitor works from scratch with a 7950 or fury but not with three
> 290X tested, is that it is possible to retrieve the values that work ?</span >
The same algorithm is used on all of those parts. The only reason there would
be different dividers selected would be if the pll limits in the vbios or the
reference clock were different. However, looking at various vbioses for those
different asics indicate that the vbios limits are the same for all of them. I
doubt they would be different on your boards. As such. that combination of
dividers seems to be disagreeable to your monitor on that specific hw. The
underlying hw implementation of the pll varies a bit from asic to asic, so the
pll selection probably needs to be tweaked a bit for that hw to be stable at
that combination as per <a href="show_bug.cgi?id=93826#c17">comment 17</a>.</pre>
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