<html> <head> <base href="https://bugs.freedesktop.org/" /> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - Tonga llvm assert since RegisterCoalescer: Need to check DstReg+SrcReg for missing undef flags" href="https://bugs.freedesktop.org/show_bug.cgi?id=94445#c8">Comment # 8</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - Tonga llvm assert since RegisterCoalescer: Need to check DstReg+SrcReg for missing undef flags" href="https://bugs.freedesktop.org/show_bug.cgi?id=94445">bug 94445</a> from <a class="email" href="mailto:adf.lists@gmail.com" title="Andy Furniss <adf.lists@gmail.com>"> Andy Furniss</a> <pre>Fixing commit = commit d3adac51fcce66e8c79b77299fef9e5f6c4c646e Author: Tom Stellard <<a href="mailto:thomas.stellard@amd.com">thomas.stellard@amd.com</a>> Date: Wed Mar 30 16:35:09 2016 +0000 AMDGPU/SI: Enable lanemask tracking in misched Summary: This results in higher register usage, but should make it easier for the compiler to hide latency. This pass is a prerequisite for some more scheduler improvements, and I think the increase register usage with this patch is acceptable, because when combined with the scheduler improvements, the total register usage will decrease. shader-db stats: 2382 shaders in 478 tests Totals: SGPRS: 48672 -> 49088 (0.85 %) VGPRS: 34148 -> 34847 (2.05 %) Code Size: 1285816 -> 1289128 (0.26 %) bytes LDS: 28 -> 28 (0.00 %) blocks Scratch: 492544 -> 573440 (16.42 %) bytes per wave Max Waves: 6856 -> 6846 (-0.15 %) Wait states: 0 -> 0 (0.00 %) Depends on D18451 Reviewers: nhaehnle, arsenm Subscribers: arsenm, llvm-commits Differential Revision: <a href="http://reviews.llvm.org/D18452">http://reviews.llvm.org/D18452</a> git-svn-id: <a href="https://llvm.org/svn/llvm-project/llvm/trunk@264876">https://llvm.org/svn/llvm-project/llvm/trunk@264876</a> 91177308-0d34-0410-b5e6-96231b3b80d8</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>