<div dir="ltr">Hi Eric,<div><br></div><div>A little nitpick below.</div><div><br></div><div>Regards</div><div>Nils<br><div class="gmail_extra"><br><div class="gmail_quote">On Fri, May 13, 2016 at 8:48 PM, Alex Deucher <span dir="ltr"><<a href="mailto:alexdeucher@gmail.com" target="_blank">alexdeucher@gmail.com</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">From: Eric Huang <<a href="mailto:JinHuiEric.Huang@amd.com">JinHuiEric.Huang@amd.com</a>><br>
<br>
Add a new sysfs entry pp_sclk_od to support sclk overdrive(OD) overclocking,<br>
the entry is read/write, the value of input/output is an integer which is the<br>
over percentage of the highest sclk.<br>
<br>
Reviewed-by: Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>><br>
Signed-off-by: Eric Huang <<a href="mailto:JinHuiEric.Huang@amd.com">JinHuiEric.Huang@amd.com</a>><br>
Signed-off-by: Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>><br>
---<br>
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 6 +++<br>
drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c | 49 +++++++++++++++++++++++<br>
drivers/gpu/drm/amd/powerplay/amd_powerplay.c | 44 ++++++++++++++++++++<br>
drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h | 2 +<br>
drivers/gpu/drm/amd/powerplay/inc/hwmgr.h | 2 +<br>
5 files changed, 103 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
index 992f00b..367dbc4 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h<br>
@@ -2335,6 +2335,12 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)<br>
#define amdgpu_dpm_force_clock_level(adev, type, level) \<br>
(adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)<br>
<br>
+#define amdgpu_dpm_get_sclk_od(adev) \<br>
+ (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)<br>
+<br>
+#define amdgpu_dpm_set_sclk_od(adev, value) \<br>
+ (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)<br>
+<br>
#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \<br>
(adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))<br>
<br>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
index 589b36e..f7ecaf4 100644<br>
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c<br>
@@ -471,6 +471,46 @@ fail:<br>
return count;<br>
}<br>
<br>
+static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,<br>
+ struct device_attribute *attr,<br>
+ char *buf)<br>
+{<br>
+ struct drm_device *ddev = dev_get_drvdata(dev);<br>
+ struct amdgpu_device *adev = ddev->dev_private;<br>
+ uint32_t value = 0;<br>
+<br>
+ if (adev->pp_enabled)<br>
+ value = amdgpu_dpm_get_sclk_od(adev);<br>
+<br>
+ return snprintf(buf, PAGE_SIZE, "%d\n", value);;<br></blockquote><div><br></div><div>Double semicolon here ^</div><div> </div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
+}<br>
+<br>
+static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,<br>
+ struct device_attribute *attr,<br>
+ const char *buf,<br>
+ size_t count)<br>
+{<br>
+ struct drm_device *ddev = dev_get_drvdata(dev);<br>
+ struct amdgpu_device *adev = ddev->dev_private;<br>
+ int ret;<br>
+ long int value;<br>
+<br>
+ ret = kstrtol(buf, 0, &value);<br>
+<br>
+ if (ret) {<br>
+ count = -EINVAL;<br>
+ goto fail;<br>
+ }<br>
+<br>
+ if (adev->pp_enabled)<br>
+ amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);<br>
+<br>
+ amdgpu_dpm_dispatch_task(adev, AMD_PP_EVENT_READJUST_POWER_STATE, NULL, NULL);<br>
+<br>
+fail:<br>
+ return count;<br>
+}<br>
+<br>
static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, amdgpu_get_dpm_state, amdgpu_set_dpm_state);<br>
static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR,<br>
amdgpu_get_dpm_forced_performance_level,<br>
@@ -492,6 +532,9 @@ static DEVICE_ATTR(pp_dpm_mclk, S_IRUGO | S_IWUSR,<br>
static DEVICE_ATTR(pp_dpm_pcie, S_IRUGO | S_IWUSR,<br>
amdgpu_get_pp_dpm_pcie,<br>
amdgpu_set_pp_dpm_pcie);<br>
+static DEVICE_ATTR(pp_sclk_od, S_IRUGO | S_IWUSR,<br>
+ amdgpu_get_pp_sclk_od,<br>
+ amdgpu_set_pp_sclk_od);<br>
<br>
static ssize_t amdgpu_hwmon_show_temp(struct device *dev,<br>
struct device_attribute *attr,<br>
@@ -1125,6 +1168,11 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)<br>
DRM_ERROR("failed to create device file pp_dpm_pcie\n");<br>
return ret;<br>
}<br>
+ ret = device_create_file(adev->dev, &dev_attr_pp_sclk_od);<br>
+ if (ret) {<br>
+ DRM_ERROR("failed to create device file pp_sclk_od\n");<br>
+ return ret;<br>
+ }<br>
}<br>
ret = amdgpu_debugfs_pm_init(adev);<br>
if (ret) {<br>
@@ -1151,6 +1199,7 @@ void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)<br>
device_remove_file(adev->dev, &dev_attr_pp_dpm_sclk);<br>
device_remove_file(adev->dev, &dev_attr_pp_dpm_mclk);<br>
device_remove_file(adev->dev, &dev_attr_pp_dpm_pcie);<br>
+ device_remove_file(adev->dev, &dev_attr_pp_sclk_od);<br>
}<br>
}<br>
<br>
diff --git a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c<br>
index 8e345bf..e0f2440 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/amd_powerplay.c<br>
+++ b/drivers/gpu/drm/amd/powerplay/amd_powerplay.c<br>
@@ -530,6 +530,10 @@ int pp_dpm_dispatch_tasks(void *handle, enum amd_pp_event event_id, void *input,<br>
case AMD_PP_EVENT_COMPLETE_INIT:<br>
ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);<br>
break;<br>
+ case AMD_PP_EVENT_READJUST_POWER_STATE:<br>
+ pp_handle->hwmgr->current_ps = pp_handle->hwmgr->boot_ps;<br>
+ ret = pem_handle_event(pp_handle->eventmgr, event_id, &data);<br>
+ break;<br>
default:<br>
break;<br>
}<br>
@@ -800,6 +804,44 @@ static int pp_dpm_print_clock_levels(void *handle,<br>
return hwmgr->hwmgr_func->print_clock_levels(hwmgr, type, buf);<br>
}<br>
<br>
+static int pp_dpm_get_sclk_od(void *handle)<br>
+{<br>
+ struct pp_hwmgr *hwmgr;<br>
+<br>
+ if (!handle)<br>
+ return -EINVAL;<br>
+<br>
+ hwmgr = ((struct pp_instance *)handle)->hwmgr;<br>
+<br>
+ PP_CHECK_HW(hwmgr);<br>
+<br>
+ if (hwmgr->hwmgr_func->get_sclk_od == NULL) {<br>
+ printk(KERN_INFO "%s was not implemented.\n", __func__);<br>
+ return 0;<br>
+ }<br>
+<br>
+ return hwmgr->hwmgr_func->get_sclk_od(hwmgr);<br>
+}<br>
+<br>
+static int pp_dpm_set_sclk_od(void *handle, uint32_t value)<br>
+{<br>
+ struct pp_hwmgr *hwmgr;<br>
+<br>
+ if (!handle)<br>
+ return -EINVAL;<br>
+<br>
+ hwmgr = ((struct pp_instance *)handle)->hwmgr;<br>
+<br>
+ PP_CHECK_HW(hwmgr);<br>
+<br>
+ if (hwmgr->hwmgr_func->set_sclk_od == NULL) {<br>
+ printk(KERN_INFO "%s was not implemented.\n", __func__);<br>
+ return 0;<br>
+ }<br>
+<br>
+ return hwmgr->hwmgr_func->set_sclk_od(hwmgr, value);<br>
+}<br>
+<br>
const struct amd_powerplay_funcs pp_dpm_funcs = {<br>
.get_temperature = pp_dpm_get_temperature,<br>
.load_firmware = pp_dpm_load_fw,<br>
@@ -822,6 +864,8 @@ const struct amd_powerplay_funcs pp_dpm_funcs = {<br>
.set_pp_table = pp_dpm_set_pp_table,<br>
.force_clock_level = pp_dpm_force_clock_level,<br>
.print_clock_levels = pp_dpm_print_clock_levels,<br>
+ .get_sclk_od = pp_dpm_get_sclk_od,<br>
+ .set_sclk_od = pp_dpm_set_sclk_od,<br>
};<br>
<br>
static int amd_pp_instance_init(struct amd_pp_init *pp_init,<br>
diff --git a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h<br>
index 50b367d..154d406 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h<br>
+++ b/drivers/gpu/drm/amd/powerplay/inc/amd_powerplay.h<br>
@@ -342,6 +342,8 @@ struct amd_powerplay_funcs {<br>
int (*set_pp_table)(void *handle, const char *buf, size_t size);<br>
int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);<br>
int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);<br>
+ int (*get_sclk_od)(void *handle);<br>
+ int (*set_sclk_od)(void *handle, uint32_t value);<br>
};<br>
<br>
struct amd_powerplay {<br>
diff --git a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h<br>
index 28f5714..37ebfa2 100644<br>
--- a/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h<br>
+++ b/drivers/gpu/drm/amd/powerplay/inc/hwmgr.h<br>
@@ -338,6 +338,8 @@ struct pp_hwmgr_func {<br>
int (*force_clock_level)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, uint32_t mask);<br>
int (*print_clock_levels)(struct pp_hwmgr *hwmgr, enum pp_clock_type type, char *buf);<br>
int (*enable_per_cu_power_gating)(struct pp_hwmgr *hwmgr, bool enable);<br>
+ int (*get_sclk_od)(struct pp_hwmgr *hwmgr);<br>
+ int (*set_sclk_od)(struct pp_hwmgr *hwmgr, uint32_t value);<br>
};<br>
<br>
struct pp_table_func {<br>
<span class="HOEnZb"><font color="#888888">--<br>
2.5.5<br>
<br>
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</font></span></blockquote></div><br></div></div></div>