<div dir="ltr"><div><div>Hi Stefan,<br><br></div>Yes, these changes do work for the Tower board!<br><br></div>-Tony<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Sat, Jun 25, 2016 at 4:53 PM, Stefan Agner <span dir="ltr"><<a href="mailto:stefan@agner.ch" target="_blank">stefan@agner.ch</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"><span class="">On 2016-06-24 12:44, Anthony Felice wrote:<br>
> This adds nodes to enable tcon0 and dcu0 for the Vybrid Tower. These<br>
> are used to drive the Vybrid Tower TWR-LCD-RGB display. Also, a node<br>
> for the nec nl4827hc19-05b panel on the TWR-LCD-RGB display has been<br>
> added.<br>
<br>
</span>So my pixel clock polarity changes which will be part of 4.7 work for<br>
Tower? I could never actually test that since I don't have the display<br>
here...<br>
<a href="https://patchwork.kernel.org/patch/8874971/" rel="noreferrer" target="_blank">https://patchwork.kernel.org/patch/8874971/</a><br>
<br>
This patch looks good to me:<br>
Acked-by: Stefan Agner <<a href="mailto:stefan@agner.ch">stefan@agner.ch</a>><br>
<br>
--<br>
Stefan<br>
<div class="HOEnZb"><div class="h5"><br>
><br>
> Signed-off-by: Anthony Felice <<a href="mailto:tony.felice@timesys.com">tony.felice@timesys.com</a>><br>
> ---<br>
> arch/arm/boot/dts/vf610-twr.dts | 48 +++++++++++++++++++++++++++++++++++++++++<br>
> 1 file changed, 48 insertions(+)<br>
><br>
> diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts<br>
> index cdc1007..ad1aff9 100644<br>
> --- a/arch/arm/boot/dts/vf610-twr.dts<br>
> +++ b/arch/arm/boot/dts/vf610-twr.dts<br>
> @@ -66,6 +66,10 @@<br>
> clock-frequency = <50000000>;<br>
> };<br>
><br>
> + panel: panel {<br>
> + compatible = "nec,nl4827hc19-05b";<br>
> + };<br>
> +<br>
> regulators {<br>
> compatible = "simple-bus";<br>
> #address-cells = <1>;<br>
> @@ -134,6 +138,13 @@<br>
> <&clks VF610_CLK_ENET_EXT>;<br>
> };<br>
><br>
> +&dcu0 {<br>
> + fsl,panel = <&panel>;<br>
> + pinctrl-names = "default";<br>
> + pinctrl-0 = <&pinctrl_dcu0>;<br>
> + status = "okay";<br>
> +};<br>
> +<br>
> &dspi0 {<br>
> bus-num = <0>;<br>
> pinctrl-names = "default";<br>
> @@ -210,6 +221,39 @@<br>
><br>
> &iomuxc {<br>
> vf610-twr {<br>
> + pinctrl_dcu0: dcu0grp {<br>
> + fsl,pins = <<br>
> + VF610_PAD_PTE0__DCU0_HSYNC 0x42<br>
> + VF610_PAD_PTE1__DCU0_VSYNC 0x42<br>
> + VF610_PAD_PTE2__DCU0_PCLK 0x42<br>
> + VF610_PAD_PTE4__DCU0_DE 0x42<br>
> + VF610_PAD_PTE5__DCU0_R0 0x42<br>
> + VF610_PAD_PTE6__DCU0_R1 0x42<br>
> + VF610_PAD_PTE7__DCU0_R2 0x42<br>
> + VF610_PAD_PTE8__DCU0_R3 0x42<br>
> + VF610_PAD_PTE9__DCU0_R4 0x42<br>
> + VF610_PAD_PTE10__DCU0_R5 0x42<br>
> + VF610_PAD_PTE11__DCU0_R6 0x42<br>
> + VF610_PAD_PTE12__DCU0_R7 0x42<br>
> + VF610_PAD_PTE13__DCU0_G0 0x42<br>
> + VF610_PAD_PTE14__DCU0_G1 0x42<br>
> + VF610_PAD_PTE15__DCU0_G2 0x42<br>
> + VF610_PAD_PTE16__DCU0_G3 0x42<br>
> + VF610_PAD_PTE17__DCU0_G4 0x42<br>
> + VF610_PAD_PTE18__DCU0_G5 0x42<br>
> + VF610_PAD_PTE19__DCU0_G6 0x42<br>
> + VF610_PAD_PTE20__DCU0_G7 0x42<br>
> + VF610_PAD_PTE21__DCU0_B0 0x42<br>
> + VF610_PAD_PTE22__DCU0_B1 0x42<br>
> + VF610_PAD_PTE23__DCU0_B2 0x42<br>
> + VF610_PAD_PTE24__DCU0_B3 0x42<br>
> + VF610_PAD_PTE25__DCU0_B4 0x42<br>
> + VF610_PAD_PTE26__DCU0_B5 0x42<br>
> + VF610_PAD_PTE27__DCU0_B6 0x42<br>
> + VF610_PAD_PTE28__DCU0_B7 0x42<br>
> + >;<br>
> + };<br>
> +<br>
> pinctrl_adc0_ad5: adc0ad5grp {<br>
> fsl,pins = <<br>
> VF610_PAD_PTC30__ADC0_SE5 0xa1<br>
> @@ -370,6 +414,10 @@<br>
> status = "okay";<br>
> };<br>
><br>
> +&tcon0 {<br>
> + status = "okay";<br>
> +};<br>
> +<br>
> &uart1 {<br>
> pinctrl-names = "default";<br>
> pinctrl-0 = <&pinctrl_uart1>;<br>
</div></div></blockquote></div><br><br clear="all"><br>-- <br><div class="gmail_signature" data-smartmail="gmail_signature"><div dir="ltr"><div><div dir="ltr"><div>Tony Felice<br>Support Engineering Manager<br></div>Timesys Corporation<br></div></div></div></div>
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