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<b><a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED NOTABUG - Wrong values returned by GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT & GL_TEXTURE_BUFFER_OFFSET_ALIGNMENT randomly breaks stuff"
href="https://bugs.freedesktop.org/show_bug.cgi?id=97305#c6">Comment # 6</a>
on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED NOTABUG - Wrong values returned by GL_UNIFORM_BUFFER_OFFSET_ALIGNMENT & GL_TEXTURE_BUFFER_OFFSET_ALIGNMENT randomly breaks stuff"
href="https://bugs.freedesktop.org/show_bug.cgi?id=97305">bug 97305</a>
from <span class="vcard"><a class="email" href="mailto:dark_sylinc@yahoo.com.ar" title="Matias N. Goldberg <dark_sylinc@yahoo.com.ar>"> <span class="fn">Matias N. Goldberg</span></a>
</span></b>
<pre>I'm back.
I only tested texture and uniform buffers, not SSBOs.
Results:
* Setting UBOs to 4 byte alignments didn't seem to matter in any way.
Performance didn't seem to be affected either. Nonetheless given that AMD
always sets it to 256; this is what I'd recommend (i.e. there could be
undocumented hw errors for edge cases?)
* Setting TBOs to non-16 byte alignments breaks in a specific pattern (i.e. 4
byte alignments produce certain glitches, 8 byte alignments produce a different
set of glitches, 12 byte alignments a different set, etc). Setting TBOs to 16
byte alignments fixes everything. I benchmarked 256-byte alignments vs 16-byte
alignments-non-256-byte and couldn't see any performance difference (the sample
kept around 46.50-47.00ms all the time).</pre>
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