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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state"
href="https://bugs.freedesktop.org/show_bug.cgi?id=98821#c4">Comment # 4</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state"
href="https://bugs.freedesktop.org/show_bug.cgi?id=98821">bug 98821</a>
from <span class="vcard"><a class="email" href="mailto:arek.rusi@gmail.com" title="Arek Ruśniak <arek.rusi@gmail.com>"> <span class="fn">Arek Ruśniak</span></a>
</span></b>
<pre>Created <span class=""><a href="attachment.cgi?id=128153" name="attach_128153" title="dmesg - revert refine uvd 6.0 clock gate feature">attachment 128153</a> <a href="attachment.cgi?id=128153&action=edit" title="dmesg - revert refine uvd 6.0 clock gate feature">[details]</a></span>
dmesg - revert refine uvd 6.0 clock gate feature</pre>
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