<html> <head> <base href="https://bugs.freedesktop.org/"> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state" href="https://bugs.freedesktop.org/show_bug.cgi?id=98821#c5">Comment # 5</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state" href="https://bugs.freedesktop.org/show_bug.cgi?id=98821">bug 98821</a> from <a class="email" href="mailto:alexdeucher@gmail.com" title="Alex Deucher <alexdeucher@gmail.com>"> Alex Deucher</a> <pre>Can you clarify the behavior you are seeing as per my questions in <a href="show_bug.cgi?id=98821#c1">comment 1</a>? Is it possible this failure is just random? I don't see why drm/amdgpu:impl vgt_flush for VI(V5) would have any affect on mclk at all. It's just adding some additional synchronization packets that mesa may already submit today. The following are likely the reason the mclk is getting stuck. [ 1.570820] failed to send message 5e ret is 0 [ 1.953147] failed to send pre message 145 ret is 0 Please use /sys/kernel/debug/dri/64/amdgpu_pm_info to verify the clocks at runtime rather than the files in sysfs.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>