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<b><a class="bz_bug_link
bz_status_NEW "
title="NEW - [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state"
href="https://bugs.freedesktop.org/show_bug.cgi?id=98821#c17">Comment # 17</a>
on <a class="bz_bug_link
bz_status_NEW "
title="NEW - [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state"
href="https://bugs.freedesktop.org/show_bug.cgi?id=98821">bug 98821</a>
from <span class="vcard"><a class="email" href="mailto:alexdeucher@gmail.com" title="Alex Deucher <alexdeucher@gmail.com>"> <span class="fn">Alex Deucher</span></a>
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<pre>I believe it was this patch that fixed it:
<a href="https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-4.10-wip&id=00cfa1ff75340cc11425085fb9f43a6b19a06568">https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-4.10-wip&id=00cfa1ff75340cc11425085fb9f43a6b19a06568</a></pre>
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