<div dir="ltr"><div>Reviewed-by: Marek Olšák <<a href="mailto:marek.olsak@amd.com">marek.olsak@amd.com</a>><br><br></div>Marek<br></div><div class="gmail_extra"><br><div class="gmail_quote">On Sun, Jul 30, 2017 at 10:18 AM, Jean Delvare <span dir="ltr"><<a href="mailto:jdelvare@suse.de" target="_blank">jdelvare@suse.de</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">As I was staring at the si_init_golden_registers code, I noticed that<br>
the Pitcairn initialization silently falls through the Cape Verde<br>
initialization, and the Oland initialization falls through the Hainan<br>
initialization. However there is no comment stating that this is<br>
intentional, and the radeon driver doesn't have any such fallthrough,<br>
so I suspect this is not supposed to happen.<br>
<br>
Signed-off-by: Jean Delvare <<a href="mailto:jdelvare@suse.de">jdelvare@suse.de</a>><br>
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")<br>
Cc: Ken Wang <<a href="mailto:Qingqing.Wang@amd.com">Qingqing.Wang@amd.com</a>><br>
Cc: Alex Deucher <<a href="mailto:alexander.deucher@amd.com">alexander.deucher@amd.com</a>><br>
Cc: "Marek Olšák" <<a href="mailto:maraeo@gmail.com">maraeo@gmail.com</a>><br>
Cc: "Christian König" <<a href="mailto:christian.koenig@amd.com">christian.koenig@amd.com</a>><br>
Cc: Flora Cui <<a href="mailto:Flora.Cui@amd.com">Flora.Cui@amd.com</a>><br>
---<br>
If the fallthroughs are really supposed to happen, comments should be<br>
added that say so. Surprisingly it doesn't seem to make any<br>
difference on my Oland card.<br>
<br>
drivers/gpu/drm/amd/amdgpu/si.<wbr>c | 2 ++<br>
1 file changed, 2 insertions(+)<br>
<br>
--- linux-4.12.orig/drivers/gpu/<wbr>drm/amd/amdgpu/si.c 2017-07-30 09:25:46.891083334 +0200<br>
+++ linux-4.12/drivers/gpu/drm/<wbr>amd/amdgpu/si.c 2017-07-30 09:45:24.350188642 +0200<br>
@@ -1385,6 +1385,7 @@ static void si_init_golden_registers(str<br>
amdgpu_program_register_<wbr>sequence(adev,<br>
pitcairn_mgcg_cgcg_init,<br>
(const u32)ARRAY_SIZE(pitcairn_mgcg_<wbr>cgcg_init));<br>
+ break;<br>
case CHIP_VERDE:<br>
amdgpu_program_register_<wbr>sequence(adev,<br>
verde_golden_registers,<br>
@@ -1409,6 +1410,7 @@ static void si_init_golden_registers(str<br>
amdgpu_program_register_<wbr>sequence(adev,<br>
oland_mgcg_cgcg_init,<br>
(const u32)ARRAY_SIZE(oland_mgcg_<wbr>cgcg_init));<br>
+ break;<br>
case CHIP_HAINAN:<br>
amdgpu_program_register_<wbr>sequence(adev,<br>
hainan_golden_registers,<br>
<span class="HOEnZb"><font color="#888888"><br>
<br>
--<br>
Jean Delvare<br>
SUSE L3 Support<br>
</font></span></blockquote></div><br></div>