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<body><span class="vcard"><a class="email" href="mailto:marta.lofstedt@intel.com" title="Marta Löfstedt <marta.lofstedt@intel.com>"> <span class="fn">Marta Löfstedt</span></a>
</span> changed
<a class="bz_bug_link
bz_status_REOPENED "
title="REOPENED - [CI] igt@prime_mmap_coherency@write - fail - Failed assertion: !(stale)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=103168">bug 103168</a>
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<th>What</th>
<th>Removed</th>
<th>Added</th>
</tr>
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<td style="text-align:right;">Resolution</td>
<td>FIXED
</td>
<td>---
</td>
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<td style="text-align:right;">Status</td>
<td>RESOLVED
</td>
<td>REOPENED
</td>
</tr>
<tr>
<td style="text-align:right;">Summary</td>
<td>[CI] igt@prime_mmap_coherency@[write-and-fail|write] - fai - Failed assertion: !(!stale)
</td>
<td>[CI] igt@prime_mmap_coherency@write - fail - Failed assertion: !(stale)
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<b><a class="bz_bug_link
bz_status_REOPENED "
title="REOPENED - [CI] igt@prime_mmap_coherency@write - fail - Failed assertion: !(stale)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=103168#c4">Comment # 4</a>
on <a class="bz_bug_link
bz_status_REOPENED "
title="REOPENED - [CI] igt@prime_mmap_coherency@write - fail - Failed assertion: !(stale)"
href="https://bugs.freedesktop.org/show_bug.cgi?id=103168">bug 103168</a>
from <span class="vcard"><a class="email" href="mailto:marta.lofstedt@intel.com" title="Marta Löfstedt <marta.lofstedt@intel.com>"> <span class="fn">Marta Löfstedt</span></a>
</span></b>
<pre>(In reply to Chris Wilson from <a href="show_bug.cgi?id=103168#c3">comment #3</a>)
<span class="quote">> Test removed in
>
> commit 22fdae38cbad3794a315bfd8d9fd833eba4a35dc
> Author: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>>
> Date: Wed Oct 11 10:51:22 2017 +0100
>
> igt/prime_mmap_coherency: Only assert correct usage of sync API
>
> Ignore the unexpected success when the CPU cache is randomly flushed
> that makes !llc appear to work without sync. It happens, the cpu cache
> is a fickle beast that we do not have sole control over. Instead limit
> the test to detect failures when the API is being adhered to.</span >
>
I agree that:
igt@prime_mmap_coherency@write-and-fail
is skipped from CI_DRM_3254 on APL-shards. However, before I realized this I
had already filed igt@prime_mmap_coherency@write for GLK-shards on this bug.
The currently latest occurrence of igt@prime_mmap_coherency@write issue is on:
<a href="https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3256/shard-glkb3/igt@prime_mmap_coherency@write.html">https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_3256/shard-glkb3/igt@prime_mmap_coherency@write.html</a>
which is after the patch was merged.</pre>
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