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Hi,<br>
<div class="moz-cite-prefix">On 09/05/2018 10:16 AM, Maxime Ripard
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:20180905071645.ibhcuq5coc6gl6k3@flea">
<pre wrap="">On Tue, Sep 04, 2018 at 12:40:44PM +0800, Icenowy Zheng wrote:
</pre>
<blockquote type="cite">
<pre wrap="">Video PLLs on A64 can be set to higher rate that it is actually
supported by HW.
Limit maximum rate to 1008 MHz. This is the maximum allowed rate by BSP
clock driver. Interestengly, user manual specifies maximum frequency to
be 600 MHz. Historically, this data was wrong in some user manuals for
other SoCs, so more faith is put in BSP clock driver.
Signed-off-by: Icenowy Zheng <a class="moz-txt-link-rfc2396E" href="mailto:icenowy@aosc.io"><icenowy@aosc.io></a>
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</blockquote>
<pre wrap="">
Applied, thanks!
Maxime
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<br>
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</pre>
</blockquote>
what source tree this patch is supposed to apply for ?<br>
I can't find the SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN_MAX
declaration in 4.19<br>
<br>
Thank you<br>
Sergey<br>
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