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      <base href="https://bugs.freedesktop.org/">
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    <body><table border="1" cellspacing="0" cellpadding="8">
        <tr>
          <th>Bug ID</th>
          <td><a class="bz_bug_link 
          bz_status_NEW "
   title="NEW - E9260 not working with recent software/firmware"
   href="https://bugs.freedesktop.org/show_bug.cgi?id=109127">109127</a>
          </td>
        </tr>

        <tr>
          <th>Summary</th>
          <td>E9260 not working with recent software/firmware
          </td>
        </tr>

        <tr>
          <th>Product</th>
          <td>DRI
          </td>
        </tr>

        <tr>
          <th>Version</th>
          <td>unspecified
          </td>
        </tr>

        <tr>
          <th>Hardware</th>
          <td>x86-64 (AMD64)
          </td>
        </tr>

        <tr>
          <th>OS</th>
          <td>Linux (All)
          </td>
        </tr>

        <tr>
          <th>Status</th>
          <td>NEW
          </td>
        </tr>

        <tr>
          <th>Severity</th>
          <td>blocker
          </td>
        </tr>

        <tr>
          <th>Priority</th>
          <td>medium
          </td>
        </tr>

        <tr>
          <th>Component</th>
          <td>DRM/AMDgpu
          </td>
        </tr>

        <tr>
          <th>Assignee</th>
          <td>dri-devel@lists.freedesktop.org
          </td>
        </tr>

        <tr>
          <th>Reporter</th>
          <td>john.alexander@datapath.co.uk
          </td>
        </tr></table>
      <p>
        <div>
        <pre>Using recent AMDGPU source code and recent firmware files for the E9260 GPU
(Polaris11, deviceID:67E8h) the GPU fails to initialise correctly.  Debugging
shows that the RLC times out entering safe mode, further debugging shows this
is because the SMU has uploaded garbage firmware.

I've had a pcie interposer/bus analyser inline with this GPU and can see that
the issue is that GTT addresses are not being translated.  When the SMU request
to load firmware is sent the PCIe read operations contain the GPU MC addresses,
not the system page addresses as they have been programmed within the gart
table.  If we shunt the firmware bo and the SMUs firmware header allocations
into VRAM rather than the GTT the firmware is correctly uploaded; the net
result is that GFX ring tests then fail with similar results; The GPU can then
be observed attempting to read from the GFX ring but the addresses used across
the PCIe bus are the MC ring addresses, not the system page addresses.</pre>
        </div>
      </p>


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