<html> <head> <base href="https://bugs.freedesktop.org/"> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - Crashes / Resets From AMDGPU / Radeon VII" href="https://bugs.freedesktop.org/show_bug.cgi?id=110674#c74">Comment # 74</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - Crashes / Resets From AMDGPU / Radeon VII" href="https://bugs.freedesktop.org/show_bug.cgi?id=110674">bug 110674</a> from <a class="email" href="mailto:sylvain.bertrand@gmail.com" title="Sylvain BERTRAND <sylvain.bertrand@gmail.com>"> Sylvain BERTRAND</a> <pre>Forcing the memory clock and voltage is not enough: the dc[en]x memory requests should be given also the highest priority in the arbiter block. I don't recall how it interacts with the dc[en]x watermarks, but they should be "disabled" or "maxed out". Basically, whatever the 3D/compute/(vcn|vce/uvd) load, the dc[en]x will always come first (due to the realtime nature of display data transmission to monitors). Oh and of course, the smu/smc should not manage the dc[en]x. Very probably, there are some smc/smu commands to do that. If the GPU did not crash with dpm disabled as a whole, the proper way to proceed would be to start from there and step by step add dpm features and see when it starts crashing. It's not a small task since dpm code paths may be scattered all over the code.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>