<html> <head> <base href="https://bugs.freedesktop.org/"> </head> <body> <div> <a class="bz_bug_link bz_status_NEW " title="NEW - Crashes / Resets From AMDGPU / Radeon VII" href="https://bugs.freedesktop.org/show_bug.cgi?id=110674#c71">Comment # 71</a> on <a class="bz_bug_link bz_status_NEW " title="NEW - Crashes / Resets From AMDGPU / Radeon VII" href="https://bugs.freedesktop.org/show_bug.cgi?id=110674">bug 110674</a> from <a class="email" href="mailto:sylvain.bertrand@gmail.com" title="Sylvain BERTRAND <sylvain.bertrand@gmail.com>"> Sylvain BERTRAND</a> <pre>On Sun, Aug 11, 2019 at 01:15:48AM +0000, <a href="mailto:bugzilla-daemon@freedesktop.org">bugzilla-daemon@freedesktop.org</a> wrote: > I think the clock dysregulation and excessive voltage/wattage are symptoms of Is there a way to configure the smu block to keep the memory clock to its max with the appropriate power/voltage? If the smu block do configure some of the vram arbiter block priority, could we tell it to keep the dc[en]x to max priority and ignore display vram watermarks? (due to the realtime requirement of monitor data transmission, I still don't understand the existence of watermarks in the first place, I would need data which proves me wrong). On my AMD TAHITI XT, the memory clock seems to be locked to the max (only 1 full hd 144Hz monitor). I recall dce6 has fancy inner-blocks configuration: I simplified it in my custom driver (something about availability of display clocks and memory bandwidth. Maybe the smu while clock/power managing breaks due this dc[en]x "fancy" inner-blocks configuration. Additionnally, never heard of 2 displays which would be driven by a common display block and being in sync. Is the sync dependant on the monitors and not the display block?? What I am missing ? The nasty displayport mst thingy? I would always set this to false.</pre> </div> <hr> You are receiving this mail because: <ul> <li>You are the assignee for the bug.</li> </ul> </body> </html>