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<b><a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [CI][RESUME] igt@gem_ctx_isolation@* - skip - Test requirement: !(gen > LAST_KNOWN_GEN), SKIP"
href="https://bugs.freedesktop.org/show_bug.cgi?id=111599#c4">Comment # 4</a>
on <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [CI][RESUME] igt@gem_ctx_isolation@* - skip - Test requirement: !(gen > LAST_KNOWN_GEN), SKIP"
href="https://bugs.freedesktop.org/show_bug.cgi?id=111599">bug 111599</a>
from <span class="vcard"><a class="email" href="mailto:martin.peres@free.fr" title="Martin Peres <martin.peres@free.fr>"> <span class="fn">Martin Peres</span></a>
</span></b>
<pre>(In reply to Chris Wilson from <a href="show_bug.cgi?id=111599#c3">comment #3</a>)
<span class="quote">> commit d17a484b3c22706b2b004ef1577f367d79235e43 (upstream/master,
> origin/master, origin/HEAD)
> Author: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>>
> Date: Wed Oct 2 12:22:29 2019 +0100
>
> i915/gem_ctx_isolation: Bump support for Tigerlake
>
> There's very little variation in non-privileged registers for Tigerlake,
> so we can mostly inherit the set from gen11. There is no whitelist at
> present, so we do not need to add any special registers.
>
> v2: Add COMMON_SLICE_CHICKEN2, GEN9_SLICE_COMMON_ECO_CHICKEN1 and a
> variety of huc readonly status registers.
>
> Bugzilla: <a class="bz_bug_link
bz_status_RESOLVED bz_closed"
title="RESOLVED FIXED - [CI][RESUME] igt@gem_ctx_isolation@* - skip - Test requirement: !(gen > LAST_KNOWN_GEN), SKIP"
href="show_bug.cgi?id=111599">https://bugs.freedesktop.org/show_bug.cgi?id=111599</a>
> Signed-off-by: Chris Wilson <<a href="mailto:chris@chris-wilson.co.uk">chris@chris-wilson.co.uk</a>>
> Cc: Mika Kuoppala <<a href="mailto:mika.kuoppala@linux.intel.com">mika.kuoppala@linux.intel.com</a>>
> Reviewed-by: Mika Kuoppala <<a href="mailto:mika.kuoppala@linux.intel.com">mika.kuoppala@linux.intel.com</a>></span >
Looks good, thanks!</pre>
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