<div dir="ltr"><div dir="ltr"><br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Sat, Feb 22, 2020 at 5:39 AM Sam Ravnborg <<a href="mailto:sam@ravnborg.org">sam@ravnborg.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Hi Kevin.<br>
<br>
On Fri, Feb 21, 2020 at 03:48:53PM +0800, Kevin Tang wrote:<br>
> From: Kevin Tang <<a href="mailto:kevin.tang@unisoc.com" target="_blank">kevin.tang@unisoc.com</a>><br>
> <br>
> DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs<br>
> which transfers the image data from a video memory buffer to an internal<br>
> LCD interface.<br>
> <br>
> Cc: Orson Zhai <<a href="mailto:orsonzhai@gmail.com" target="_blank">orsonzhai@gmail.com</a>><br>
> Cc: Baolin Wang <<a href="mailto:baolin.wang@linaro.org" target="_blank">baolin.wang@linaro.org</a>><br>
> Cc: Chunyan Zhang <<a href="mailto:zhang.lyra@gmail.com" target="_blank">zhang.lyra@gmail.com</a>><br>
> Signed-off-by: Kevin Tang <<a href="mailto:kevin.tang@unisoc.com" target="_blank">kevin.tang@unisoc.com</a>><br>
> ---<br>
> .../devicetree/bindings/display/sprd/dpu.yaml | 85 ++++++++++++++++++++++<br>
> 1 file changed, 85 insertions(+)<br>
> create mode 100644 Documentation/devicetree/bindings/display/sprd/dpu.yaml<br>
> <br>
> diff --git a/Documentation/devicetree/bindings/display/sprd/dpu.yaml b/Documentation/devicetree/bindings/display/sprd/dpu.yaml<br>
> new file mode 100644<br>
> index 0000000..7695d94<br>
> --- /dev/null<br>
> +++ b/Documentation/devicetree/bindings/display/sprd/dpu.yaml<br>
> @@ -0,0 +1,85 @@<br>
> +# SPDX-License-Identifier: GPL-2.0<br>
> +%YAML 1.2<br>
> +---<br>
> +$id: <a href="http://devicetree.org/schemas/display/sprd/dpu.yaml#" rel="noreferrer" target="_blank">http://devicetree.org/schemas/display/sprd/dpu.yaml#</a><br>
> +$schema: <a href="http://devicetree.org/meta-schemas/core.yaml#" rel="noreferrer" target="_blank">http://devicetree.org/meta-schemas/core.yaml#</a><br>
> +<br>
> +title: Unisoc SoC Display Processor Unit (DPU)<br>
> +<br>
> +maintainers:<br>
> + - David Airlie <<a href="mailto:airlied@linux.ie" target="_blank">airlied@linux.ie</a>><br>
> + - Daniel Vetter <<a href="mailto:daniel@ffwll.ch" target="_blank">daniel@ffwll.ch</a>><br>
> + - Rob Herring <<a href="mailto:robh%2Bdt@kernel.org" target="_blank">robh+dt@kernel.org</a>><br>
> + - Mark Rutland <<a href="mailto:mark.rutland@arm.com" target="_blank">mark.rutland@arm.com</a>><br>
> +<br>
> +description: |<br>
> + DPU (Display Processor Unit) is the Display Controller for the Unisoc SoCs<br>
> + which transfers the image data from a video memory buffer to an internal<br>
> + LCD interface.<br>
> +<br>
> +properties:<br>
> + compatible:<br>
> + const: sprd,sharkl3-dpu<br>
> +<br>
> + reg:<br>
> + maxItems: 1<br>
> + description:<br>
> + Physical base address and length of the DPU registers set<br>
> +<br>
> + interrupts:<br>
> + maxItems: 1<br>
> + description:<br>
> + The interrupt signal from DPU<br>
> +<br>
> + clocks:<br>
> + minItems: 2<br>
Should this be maxItems: 2?<br>
That would imply minItems: 2.<br></blockquote><div>We need minItems: 2, one is for display controller, one is for dpi clock</div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<br>
<br>
> +<br>
> + clock-names:<br>
> + items:<br>
> + - const: clk_src_128m<br>
> + - const: clk_src_384m<br>
> +<br>
> + power-domains:<br>
> + description: A phandle to DPU power domain node.<br>
> +<br>
> + iommus:<br>
> + description: A phandle to DPU iommu node.<br>
> +<br>
> + port:<br>
> + type: object<br>
> + description:<br>
> + A port node with endpoint definitions as defined in<br>
> + Documentation/devicetree/bindings/media/video-interfaces.txt.<br>
> + That port should be the output endpoint, usually output to<br>
> + the associated DSI.<br>
> +<br>
> +required:<br>
> + - compatible<br>
> + - reg<br>
> + - interrupts<br>
> + - clocks<br>
> + - clock-names<br>
> + - port<br>
> +<br>
> +additionalProperties: false<br>
> +<br>
> +examples:<br>
> + - |<br>
> + #include <dt-bindings/interrupt-controller/arm-gic.h><br>
> + #include <dt-bindings/clock/sprd,sc9860-clk.h><br>
> + dpu: dpu@0x63000000 {<br>
> + compatible = "sprd,sharkl3-dpu";<br>
> + reg = <0x0 0x63000000 0x0 0x1000>;<br>
> + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;<br>
> + clock-names = "clk_src_128m",<br>
> + "clk_src_384m";<br>
> +<br>
> + clocks = <&pll CLK_TWPLL_128M>,<br>
> + <&pll CLK_TWPLL_384M>;<br>
> +<br>
> + dpu_port: port {<br>
> + dpu_out: endpoint {<br>
> + remote-endpoint = <&dsi_in>;<br>
> + };<br>
> + };<br>
> + };<br>
Did this example pass dt_binding_check with no warnings?<br>
I wonder how the reg property could avoid generating warnings as the<br>
upper node do not have #address_cells, #node_cells<br></blockquote><div>Yes, pass dt_binding_check with no warnings
</div><div>Because our display controller is under ahb bus or apb bus, parent node have defined "<span style="color:rgb(0,0,0)">address-cells</span>" and "<span style="color:rgb(0,0,0)">size-cells</span>"</div><div>So subdev is omitted</div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<br>
Sam<br>
</blockquote></div></div>