<div dir="ltr">Thanks for the patch.<br>Applied to drm-misc-next.<br></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Tue, 31 Dec 2019 at 14:43, Tian Tao <<a href="mailto:tiantao6@hisilicon.com">tiantao6@hisilicon.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Add the three new pll config for corresponding resolution 1440x900 and<br>
1600x900, 640x480 for hibmc<br>
<br>
Signed-off-by: Tian Tao <<a href="mailto:tiantao6@hisilicon.com" target="_blank">tiantao6@hisilicon.com</a>><br>
Signed-off-by: Gong junjie <<a href="mailto:gongjunjie2@huawei.com" target="_blank">gongjunjie2@huawei.com</a>><br>
---<br>
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c | 3 +++<br>
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h | 2 ++<br>
2 files changed, 5 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c<br>
index f1ce6cb..6bf4334 100644<br>
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c<br>
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_de.c<br>
@@ -40,6 +40,7 @@ struct hibmc_dislay_pll_config {<br>
};<br>
<br>
static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {<br>
+ {640, 480, CRT_PLL1_HS_25MHZ, CRT_PLL2_HS_25MHZ},<br>
{800, 600, CRT_PLL1_HS_40MHZ, CRT_PLL2_HS_40MHZ},<br>
{1024, 768, CRT_PLL1_HS_65MHZ, CRT_PLL2_HS_65MHZ},<br>
{1152, 864, CRT_PLL1_HS_80MHZ_1152, CRT_PLL2_HS_80MHZ},<br>
@@ -47,6 +48,8 @@ static const struct hibmc_dislay_pll_config hibmc_pll_table[] = {<br>
{1280, 720, CRT_PLL1_HS_74MHZ, CRT_PLL2_HS_74MHZ},<br>
{1280, 960, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},<br>
{1280, 1024, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},<br>
+ {1440, 900, CRT_PLL1_HS_106MHZ, CRT_PLL2_HS_106MHZ},<br>
+ {1600, 900, CRT_PLL1_HS_108MHZ, CRT_PLL2_HS_108MHZ},<br>
{1600, 1200, CRT_PLL1_HS_162MHZ, CRT_PLL2_HS_162MHZ},<br>
{1920, 1080, CRT_PLL1_HS_148MHZ, CRT_PLL2_HS_148MHZ},<br>
{1920, 1200, CRT_PLL1_HS_193MHZ, CRT_PLL2_HS_193MHZ},<br>
diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h<br>
index 9b7e859..17b30c3 100644<br>
--- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h<br>
+++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h<br>
@@ -179,6 +179,7 @@<br>
#define CRT_PLL1_HS_74MHZ 0x23941dc2<br>
#define CRT_PLL1_HS_80MHZ 0x23941001<br>
#define CRT_PLL1_HS_80MHZ_1152 0x23540fc2<br>
+#define CRT_PLL1_HS_106MHZ 0x237C1641<br>
#define CRT_PLL1_HS_108MHZ 0x23b41b01<br>
#define CRT_PLL1_HS_162MHZ 0x23480681<br>
#define CRT_PLL1_HS_148MHZ 0x23541dc2<br>
@@ -191,6 +192,7 @@<br>
#define CRT_PLL2_HS_78MHZ 0x50E147AE<br>
#define CRT_PLL2_HS_74MHZ 0x602B6AE7<br>
#define CRT_PLL2_HS_80MHZ 0x70000000<br>
+#define CRT_PLL2_HS_106MHZ 0x0075c28f<br>
#define CRT_PLL2_HS_108MHZ 0x80000000<br>
#define CRT_PLL2_HS_162MHZ 0xA0000000<br>
#define CRT_PLL2_HS_148MHZ 0xB0CCCCCD<br>
-- <br>
2.7.4<br>
<br>
</blockquote></div>