<div dir="ltr">Reviewed-by: Caz Yokoyama <<a href="mailto:caz@caztech.com">caz@caztech.com</a>><br><div>-caz</div><div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">On Fri, Jun 24, 2022 at 2:04 PM Matt Roper <<a href="mailto:matthew.d.roper@intel.com" target="_blank">matthew.d.roper@intel.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">We've been introducing new registers with a mix of "XEHP_"<br>
(architecture) and "XEHPSDV_" (platform) prefixes. For consistency,<br>
let's settle on "XEHP_" as the preferred form.<br>
<br>
XEHPSDV_RP_STATE_CAP stays with its current name since that's truly a<br>
platform-specific register and not something that applies to the Xe_HP<br>
architecture as a whole.<br>
<br>
Signed-off-by: Matt Roper <<a href="mailto:matthew.d.roper@intel.com" target="_blank">matthew.d.roper@intel.com</a>><br>
---<br>
drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 4 ++--<br>
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 8 ++++----<br>
drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c | 4 ++--<br>
drivers/gpu/drm/i915/gt/intel_region_lmem.c | 8 ++++----<br>
drivers/gpu/drm/i915/i915_reg.h | 6 +++---<br>
5 files changed, 15 insertions(+), 15 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c<br>
index e63de9c06596..166d0a4b9e8c 100644<br>
--- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c<br>
+++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c<br>
@@ -836,8 +836,8 @@ i915_gem_stolen_lmem_setup(struct drm_i915_private *i915, u16 type,<br>
} else {<br>
resource_size_t lmem_range;<br>
<br>
- lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF;<br>
- lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;<br>
+ lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHP_TILE0_ADDR_RANGE) & 0xFFFF;<br>
+ lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;<br>
lmem_size *= SZ_1G;<br>
}<br>
<br>
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h<br>
index 61815b6e87de..37c1095d8603 100644<br>
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h<br>
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h<br>
@@ -324,11 +324,11 @@<br>
<br>
#define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4)<br>
<br>
-#define XEHPSDV_TILE0_ADDR_RANGE _MMIO(0x4900)<br>
-#define XEHPSDV_TILE_LMEM_RANGE_SHIFT 8<br>
+#define XEHP_TILE0_ADDR_RANGE _MMIO(0x4900)<br>
+#define XEHP_TILE_LMEM_RANGE_SHIFT 8<br>
<br>
-#define XEHPSDV_FLAT_CCS_BASE_ADDR _MMIO(0x4910)<br>
-#define XEHPSDV_CCS_BASE_SHIFT 8<br>
+#define XEHP_FLAT_CCS_BASE_ADDR _MMIO(0x4910)<br>
+#define XEHP_CCS_BASE_SHIFT 8<br>
<br>
#define GAMTARBMODE _MMIO(0x4a08)<br>
#define ARB_MODE_BWGTLB_DISABLE (1 << 9)<br>
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c<br>
index ae8a8f725f01..73a8b46e0234 100644<br>
--- a/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c<br>
+++ b/drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.c<br>
@@ -679,7 +679,7 @@ static ssize_t media_RP0_freq_mhz_show(struct device *dev,<br>
u32 val;<br>
int err;<br>
<br>
- err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,<br>
+ err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,<br>
PCODE_MBOX_FC_SC_READ_FUSED_P0,<br>
PCODE_MBOX_DOMAIN_MEDIAFF, &val);<br>
<br>
@@ -700,7 +700,7 @@ static ssize_t media_RPn_freq_mhz_show(struct device *dev,<br>
u32 val;<br>
int err;<br>
<br>
- err = snb_pcode_read_p(gt->uncore, XEHPSDV_PCODE_FREQUENCY_CONFIG,<br>
+ err = snb_pcode_read_p(gt->uncore, XEHP_PCODE_FREQUENCY_CONFIG,<br>
PCODE_MBOX_FC_SC_READ_FUSED_PN,<br>
PCODE_MBOX_DOMAIN_MEDIAFF, &val);<br>
<br>
diff --git a/drivers/gpu/drm/i915/gt/intel_region_lmem.c b/drivers/gpu/drm/i915/gt/intel_region_lmem.c<br>
index 2ff448047020..d09b996a9759 100644<br>
--- a/drivers/gpu/drm/i915/gt/intel_region_lmem.c<br>
+++ b/drivers/gpu/drm/i915/gt/intel_region_lmem.c<br>
@@ -105,12 +105,12 @@ static struct intel_memory_region *setup_lmem(struct intel_gt *gt)<br>
resource_size_t lmem_range;<br>
u64 tile_stolen, flat_ccs_base;<br>
<br>
- lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHPSDV_TILE0_ADDR_RANGE) & 0xFFFF;<br>
- lmem_size = lmem_range >> XEHPSDV_TILE_LMEM_RANGE_SHIFT;<br>
+ lmem_range = intel_gt_mcr_read_any(&i915->gt0, XEHP_TILE0_ADDR_RANGE) & 0xFFFF;<br>
+ lmem_size = lmem_range >> XEHP_TILE_LMEM_RANGE_SHIFT;<br>
lmem_size *= SZ_1G;<br>
<br>
- flat_ccs_base = intel_gt_mcr_read_any(gt, XEHPSDV_FLAT_CCS_BASE_ADDR);<br>
- flat_ccs_base = (flat_ccs_base >> XEHPSDV_CCS_BASE_SHIFT) * SZ_64K;<br>
+ flat_ccs_base = intel_gt_mcr_read_any(gt, XEHP_FLAT_CCS_BASE_ADDR);<br>
+ flat_ccs_base = (flat_ccs_base >> XEHP_CCS_BASE_SHIFT) * SZ_64K;<br>
<br>
/* FIXME: Remove this when we have small-bar enabled */<br>
if (pci_resource_len(pdev, 2) < lmem_size) {<br>
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h<br>
index cf5e16abf6c7..643d7f020a4a 100644<br>
--- a/drivers/gpu/drm/i915/i915_reg.h<br>
+++ b/drivers/gpu/drm/i915/i915_reg.h<br>
@@ -6767,12 +6767,12 @@<br>
#define DG1_UNCORE_GET_INIT_STATUS 0x0<br>
#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1<br>
#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23<br>
-#define XEHPSDV_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */<br>
-/* XEHPSDV_PCODE_FREQUENCY_CONFIG sub-commands (param1) */<br>
+#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* xehpsdv, pvc */<br>
+/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */<br>
#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0<br>
#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1<br>
/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */<br>
-/* XEHPSDV_PCODE_FREQUENCY_CONFIG param2 */<br>
+/* XEHP_PCODE_FREQUENCY_CONFIG param2 */<br>
#define PCODE_MBOX_DOMAIN_NONE 0x0<br>
#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3<br>
#define GEN6_PCODE_DATA _MMIO(0x138128)<br>
-- <br>
2.36.1<br>
<br>
</blockquote></div><br clear="all"><div><br></div>-- <br><div dir="ltr"><div dir="ltr"><div><div dir="ltr"><div><div dir="ltr"><div><div dir="ltr"><div><div dir="ltr"><div>-caz, caz at caztech dot com, 503-six one zero - five six nine nine(m)<br></div></div></div></div></div></div></div></div></div></div></div>