<div dir="ltr"><span style="color:rgb(32,33,36);font-family:Roboto,Arial,sans-serif;font-size:13px;letter-spacing:0.185714px">Reviewed-by: Rock Chiu </span><a target="_self" style="margin:0px;border:0px;font-family:Roboto,Arial,sans-serif;vertical-align:baseline;outline-width:0px;font-size:13px;letter-spacing:0.185714px"><span class="gmail-ng-star-inserted"></span></a><a rel="noopener noreferrer nofollow" class="gmail-keep-focus-ring" target="_self" href="mailto:rock.chiu@paradetech.corp-partner.google.com" style="margin:0px;border:0px;font-weight:inherit;font-style:inherit;font-family:inherit;vertical-align:baseline;text-decoration-line:none"><span style="margin:0px;border:0px;font-weight:inherit;font-style:inherit;font-family:inherit;vertical-align:baseline;outline-width:0px">rock.chiu@paradetech.corp-partner.google.com</span></a><div><br clear="all"><div><div dir="ltr" class="gmail_signature" data-smartmail="gmail_signature"><div dir="ltr">Rock Chiu</div></div></div><br></div></div><br><div class="gmail_quote"><div dir="ltr" class="gmail_attr">Hsin-Yi Wang <<a href="mailto:hsinyi@chromium.org">hsinyi@chromium.org</a>> 於 2022年8月15日 週一 下午5:39寫道：<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">The double reset power-on sequence is a workaround for the hardware<br>
flaw in some chip that SPI Clock output glitch and cause internal MPU<br>
unable to read firmware correctly. The sequence is suggested in ps8640<br>
application note.<br>
<br>
Signed-off-by: Hsin-Yi Wang <<a href="mailto:hsinyi@chromium.org" target="_blank">hsinyi@chromium.org</a>><br>
---<br>
 drivers/gpu/drm/bridge/parade-ps8640.c | 5 +++++<br>
 1 file changed, 5 insertions(+)<br>
<br>
diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c<br>
index 49107a6cdac18..d7483c13c569b 100644<br>
--- a/drivers/gpu/drm/bridge/parade-ps8640.c<br>
+++ b/drivers/gpu/drm/bridge/parade-ps8640.c<br>
@@ -375,6 +375,11 @@ static int __maybe_unused ps8640_resume(struct device *dev)<br>
        gpiod_set_value(ps_bridge->gpio_reset, 1);<br>
        usleep_range(2000, 2500);<br>
        gpiod_set_value(ps_bridge->gpio_reset, 0);<br>
+       /* Double reset for T4 and T5 */<br>
+       msleep(50);<br>
+       gpiod_set_value(ps_bridge->gpio_reset, 1);<br>
+       msleep(50);<br>
+       gpiod_set_value(ps_bridge->gpio_reset, 0);<br>
<br>
        /*<br>
         * Mystery 200 ms delay for the "MCU to be ready". It's unclear if<br>
-- <br>
2.37.1.595.g718a3a8f04-goog<br>
<br>
</blockquote></div>