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<p class="MsoNormal"><span style="mso-fareast-language:EN-US">Hi
Marek,<br>
</span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US">The
genmask of regsiter SSCR, BPCR & others were setted accordly
to the chipset stm32f4.</span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US">You
can see more details on page 493 of reference manual RM0090:</span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"><a
href="https://www.st.com/resource/en/reference_manual/DM00031020-.pdf"
class="moz-txt-link-freetext">https://www.st.com/resource/en/reference_manual/DM00031020-.pdf</a></span></p>
<p>With future hardware, all of these registers will aligned on
16bits.<br>
</p>
<p>I would like to know if you use a display which resolution exceed
2048.<br>
</p>
<p>Best regards<br>
</p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"
lang="EN-US">Yannick Fertré <br>
</span></p>
<p class="MsoNormal"><span style="mso-fareast-language:EN-US"
lang="EN-US"><br>
</span></p>
<div class="moz-cite-prefix">On 10/14/22 14:17, Yannick FERTRE
wrote:<br>
</div>
<blockquote type="cite"
cite="mid:93a77911-e9b2-d2e1-4fff-41f63c87376b@foss.st.com">Hi
Marek, <br>
<br>
thanks for the patch. <br>
<br>
Reviewed-by: Yannick Fertre <a class="moz-txt-link-rfc2396E"
href="mailto:yannick.fertre@foss.st.com"><yannick.fertre@foss.st.com></a>
<br>
<br>
On 10/12/22 01:10, Marek Vasut wrote: <br>
<blockquote type="cite">STM32MP15xx RM0436 Rev 6 "35.7.3 LTDC
synchronization size configuration <br>
register (LTDC_SSCR)" on page 1784 and onward indicates VSH and
similar <br>
bits are all [11:0] instead of [10:0] wide. Fix this. <br>
<br>
[1] <a class="moz-txt-link-freetext"
href="https://www.st.com/resource/en/reference_manual/DM00327659-.pdf">https://www.st.com/resource/en/reference_manual/DM00327659-.pdf</a>
<br>
<br>
Fixes: b759012c5fa7 ("drm/stm: Add STM32 LTDC driver") <br>
Signed-off-by: Marek Vasut <a class="moz-txt-link-rfc2396E"
href="mailto:marex@denx.de"><marex@denx.de></a> <br>
--- <br>
Cc: Alexandre Torgue <a class="moz-txt-link-rfc2396E"
href="mailto:alexandre.torgue@foss.st.com"><alexandre.torgue@foss.st.com></a>
<br>
Cc: Antonio Borneo <a class="moz-txt-link-rfc2396E"
href="mailto:antonio.borneo@foss.st.com"><antonio.borneo@foss.st.com></a>
<br>
Cc: Benjamin Gaignard <a class="moz-txt-link-rfc2396E"
href="mailto:benjamin.gaignard@foss.st.com"><benjamin.gaignard@foss.st.com></a>
<br>
Cc: Maxime Coquelin <a class="moz-txt-link-rfc2396E"
href="mailto:mcoquelin.stm32@gmail.com"><mcoquelin.stm32@gmail.com></a>
<br>
Cc: Philippe Cornu <a class="moz-txt-link-rfc2396E"
href="mailto:philippe.cornu@foss.st.com"><philippe.cornu@foss.st.com></a>
<br>
Cc: Sam Ravnborg <a class="moz-txt-link-rfc2396E"
href="mailto:sam@ravnborg.org"><sam@ravnborg.org></a> <br>
Cc: Vincent Abriou <a class="moz-txt-link-rfc2396E"
href="mailto:vincent.abriou@foss.st.com"><vincent.abriou@foss.st.com></a>
<br>
Cc: Yannick Fertre <a class="moz-txt-link-rfc2396E"
href="mailto:yannick.fertre@foss.st.com"><yannick.fertre@foss.st.com></a>
<br>
Cc: <a class="moz-txt-link-abbreviated moz-txt-link-freetext"
href="mailto:linux-arm-kernel@lists.infradead.org">linux-arm-kernel@lists.infradead.org</a>
<br>
Cc: <a class="moz-txt-link-abbreviated moz-txt-link-freetext"
href="mailto:linux-stm32@st-md-mailman.stormreply.com">linux-stm32@st-md-mailman.stormreply.com</a>
<br>
To: <a class="moz-txt-link-abbreviated moz-txt-link-freetext"
href="mailto:dri-devel@lists.freedesktop.org">dri-devel@lists.freedesktop.org</a>
<br>
--- <br>
drivers/gpu/drm/stm/ltdc.c | 8 ++++---- <br>
1 file changed, 4 insertions(+), 4 deletions(-) <br>
<br>
diff --git a/drivers/gpu/drm/stm/ltdc.c
b/drivers/gpu/drm/stm/ltdc.c <br>
index 03c6becda795c..639ed00b44a57 100644 <br>
--- a/drivers/gpu/drm/stm/ltdc.c <br>
+++ b/drivers/gpu/drm/stm/ltdc.c <br>
@@ -111,16 +111,16 @@ <br>
#define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /*
L1 Flexible Pixel Format 1 */ <br>
/* Bit definitions */ <br>
-#define SSCR_VSH GENMASK(10, 0) /* Vertical
Synchronization Height */ <br>
+#define SSCR_VSH GENMASK(11, 0) /* Vertical
Synchronization Height */ <br>
#define SSCR_HSW GENMASK(27, 16) /* Horizontal
Synchronization Width */ <br>
-#define BPCR_AVBP GENMASK(10, 0) /* Accumulated
Vertical Back Porch */ <br>
+#define BPCR_AVBP GENMASK(11, 0) /* Accumulated Vertical
Back Porch */ <br>
#define BPCR_AHBP GENMASK(27, 16) /* Accumulated
Horizontal Back Porch */ <br>
-#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active
Height */ <br>
+#define AWCR_AAH GENMASK(11, 0) /* Accumulated Active
Height */ <br>
#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active
Width */ <br>
-#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ <br>
+#define TWCR_TOTALH GENMASK(11, 0) /* TOTAL Height */ <br>
#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ <br>
#define GCR_LTDCEN BIT(0) /* LTDC ENable */ <br>
</blockquote>
</blockquote>
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