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<p>Hi Andi,<br>
</p>
<div class="moz-cite-prefix">On 7/21/2023 6:15 PM, Andi Shyti wrote:<br>
</div>
<blockquote type="cite"
cite="mid:20230721161514.818895-7-andi.shyti@linux.intel.com">
<pre class="moz-quote-pre" wrap="">Just a trivial refactoring for reducing the number of code
duplicate. This will come at handy in the next commits.
Meantime, propagate the error to the above layers if we fail to
emit the pipe control.
Signed-off-by: Andi Shyti <a class="moz-txt-link-rfc2396E" href="mailto:andi.shyti@linux.intel.com"><andi.shyti@linux.intel.com></a>
Cc: <a class="moz-txt-link-rfc2396E" href="mailto:stable@vger.kernel.org"><stable@vger.kernel.org></a> # v5.8+
---
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 47 +++++++++++++-----------
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 139a7e69f5c4d..5e19b45a5cabe 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -7,6 +7,7 @@
#include "i915_drv.h"
#include "intel_engine_regs.h"
#include "intel_gpu_commands.h"
+#include "intel_gt_print.h"
#include "intel_lrc.h"
#include "intel_ring.h"
@@ -189,23 +190,30 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
return cs;
}
+static int gen12_emit_pipe_control_cs(struct i915_request *rq, u32 bit_group_0,
+ u32 bit_group_1, u32 offset)
+{
+ u32 *cs;
+
+ cs = intel_ring_begin(rq, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1,
+ LRC_PPHWSP_SCRATCH_ADDR);
+ intel_ring_advance(rq, cs);
+
+ return 0;
+}
+
static int mtl_dummy_pipe_control(struct i915_request *rq)
{
/* Wa_14016712196 */
if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
- u32 *cs;
-
- /* dummy PIPE_CONTROL + depth flush */
- cs = intel_ring_begin(rq, 6);
- if (IS_ERR(cs))
- return PTR_ERR(cs);
- cs = gen12_emit_pipe_control(cs,
- 0,
- PIPE_CONTROL_DEPTH_CACHE_FLUSH,
- LRC_PPHWSP_SCRATCH_ADDR);
- intel_ring_advance(rq, cs);
- }
+ IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0))
+ return gen12_emit_pipe_control_cs(rq, 0,
+ PIPE_CONTROL_DEPTH_CACHE_FLUSH,
+ LRC_PPHWSP_SCRATCH_ADDR);</pre>
</blockquote>
<p>Don't think this will get backported to 5.8+. I think mtl
introduced after that.</p>
<p>If that is not an issue for rest of the series and then <br>
</p>
<pre class="moz-quote-pre" wrap=""><code style="padding: 0px; tab-size: 8;" class="hljs diff language-diff">Reviewed-by: Nirmoy Das <a class="moz-txt-link-rfc2396E" href="mailto:nirmoy.das@intel.com"><nirmoy.das@intel.com></a>
Regards,
Nirmoy
</code></pre>
<p></p>
<p><br>
</p>
<blockquote type="cite"
cite="mid:20230721161514.818895-7-andi.shyti@linux.intel.com">
<pre class="moz-quote-pre" wrap="">
return 0;
}
@@ -222,7 +230,6 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
u32 bit_group_0 = 0;
u32 bit_group_1 = 0;
int err;
- u32 *cs;
err = mtl_dummy_pipe_control(rq);
if (err)
@@ -256,13 +263,11 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
else if (engine->class == COMPUTE_CLASS)
bit_group_1 &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
- cs = intel_ring_begin(rq, 6);
- if (IS_ERR(cs))
- return PTR_ERR(cs);
-
- cs = gen12_emit_pipe_control(cs, bit_group_0, bit_group_1,
- LRC_PPHWSP_SCRATCH_ADDR);
- intel_ring_advance(rq, cs);
+ err = gen12_emit_pipe_control_cs(rq, bit_group_0, bit_group_1,
+ LRC_PPHWSP_SCRATCH_ADDR);
+ if (err)
+ gt_warn(engine->gt,
+ "Failed to emit flush pipe control\n");
}
if (mode & EMIT_INVALIDATE) {
</pre>
</blockquote>
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