<pre>
Hi CK,

Gentle ping for this patch, if there is anything I need to modify,
please kindly let me know.

Thanks.


On Wed, 2023-08-23 at 17:20 +0800, Shuijing Li wrote:
> Support IGT (Intel GPU Tools) in Mediatek DSI driver.
> According to the description of MIPI Alliance Specification for D-
> PHY
> Version 1.1, the maximum supported data rate is 1.5Gbps, so add
> mode_valid
> callback to dsi bridge to filter out the data rate exceeding the
> Specification.
>
> Signed-off-by: Shuijing Li <shuijing.li@mediatek.com>
> ---
> Changes in v2:
> Correct descriptions of title and commit message.
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c
> b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 7d5250351193..a494e04f0ddf 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -806,6 +806,25 @@ static void
> mtk_dsi_bridge_atomic_post_disable(struct drm_bridge *bridge,
> mtk_dsi_poweroff(dsi);
> }
>
> +static enum drm_mode_status
> +mtk_dsi_bridge_mode_valid(struct drm_bridge *bridge,
> + const struct drm_display_info *info,
> + const struct drm_display_mode *mode)
> +{
> +struct mtk_dsi *dsi = bridge_to_dsi(bridge);
> +u32 bpp;
> +
> +if (dsi->format == MIPI_DSI_FMT_RGB565)
> +bpp = 16;
> +else
> +bpp = 24;
> +
> +if (mode->clock * bpp / dsi->lanes > 1500000)
> +return MODE_CLOCK_HIGH;
> +
> +return MODE_OK;
> +}
> +
> static const struct drm_bridge_funcs mtk_dsi_bridge_funcs = {
> .attach = mtk_dsi_bridge_attach,
> .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
> @@ -815,6 +834,7 @@ static const struct drm_bridge_funcs
> mtk_dsi_bridge_funcs = {
> .atomic_pre_enable = mtk_dsi_bridge_atomic_pre_enable,
> .atomic_post_disable = mtk_dsi_bridge_atomic_post_disable,
> .atomic_reset = drm_atomic_helper_bridge_reset,
> +.mode_valid = mtk_dsi_bridge_mode_valid,
> .mode_set = mtk_dsi_bridge_mode_set,
> };
>

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