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<p class="MsoNormal">Hi Christian,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">I go back this old email to ask a question.<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Quote from your email:<o:p></o:p></p>
<p class="MsoNormal">“Those ranges can then be used to implement the SVM feature required for higher level APIs and not something you need at the UAPI or even inside the low level kernel memory management.”<o:p></o:p></p>
<p class="MsoNormal">“SVM is a high level concept of OpenCL, Cuda, ROCm etc.. This should not have any influence on the design of the kernel UAPI.”<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal"><span class="ui-provider">There are two category of SVM:<o:p></o:p></span></p>
<ol style="margin-top:0cm" start="1" type="1">
<li class="MsoListParagraph" style="margin-left:0cm;mso-list:l0 level1 lfo1"><span class="ui-provider">driver svm allocator: this is implemented in user space, i.g., cudaMallocManaged (cuda) or zeMemAllocShared (L0) or clSVMAlloc(openCL). Intel already have
gem_create/vm_bind in xekmd and our umd implemented clSVMAlloc and zeMemAllocShared on top of gem_create/vm_bind.
</span>Range A..B of the process address space is mapped into a range C..D of the GPU address space, exactly as you said.<span class="ui-provider"><o:p></o:p></span></li><li class="MsoListParagraph" style="margin-left:0cm;mso-list:l0 level1 lfo1"><span class="ui-provider">system svm allocator: This doesn’t introduce extra driver API for memory allocation. Any valid CPU virtual address can be used directly transparently in
a GPU program without any extra driver API call. Quote from kernel Documentation/vm/hmm.hst: “Any application memory region (private anonymous, shared memory, or regular file backed memory) can be used by a device transparently” and “</span><span style="color:black">to
share the address space by duplicating the CPU page table in the device page table so the same address points to the same physical memory for any valid main memory address in the process address space</span><span class="ui-provider">”. In system svm allocator,
we don’t need that A..B C..D mapping.</span><span class="ui-provider"><o:p></o:p></span></li></ol>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">It looks like you were talking of 1). Were you?<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Oak<o:p></o:p></p>
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<p class="MsoNormal"><b><span lang="EN-US">From:</span></b><span lang="EN-US"> Christian König <christian.koenig@amd.com>
<br>
<b>Sent:</b> Wednesday, January 24, 2024 3:33 AM<br>
<b>To:</b> Zeng, Oak <oak.zeng@intel.com>; Danilo Krummrich <dakr@redhat.com>; Dave Airlie <airlied@redhat.com>; Daniel Vetter <daniel@ffwll.ch>; Felix Kuehling <felix.kuehling@amd.com><br>
<b>Cc:</b> Welty, Brian <brian.welty@intel.com>; dri-devel@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Bommu, Krishnaiah <krishnaiah.bommu@intel.com>; Ghimiray, Himal Prasad <himal.prasad.ghimiray@intel.com>; Thomas.Hellstrom@linux.intel.com; Vishwanathapura,
Niranjana <niranjana.vishwanathapura@intel.com>; Brost, Matthew <matthew.brost@intel.com>; Gupta, saurabhg <saurabhg.gupta@intel.com><br>
<b>Subject:</b> Re: Making drm_gpuvm work across gpu devices<o:p></o:p></span></p>
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<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Am 23.01.24 um 20:37 schrieb Zeng, Oak:<br>
<br>
<o:p></o:p></p>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<p class="MsoNormal">[SNIP] <o:p></o:p></p>
<pre><o:p> </o:p></pre>
<pre>Yes most API are per device based.<o:p></o:p></pre>
<pre><o:p> </o:p></pre>
<pre>One exception I know is actually the kfd SVM API. If you look at the svm_ioctl function, it is per-process based. Each kfd_process represent a process across N gpu devices.<o:p></o:p></pre>
</blockquote>
<p class="MsoNormal"><br>
Yeah and that was a big mistake in my opinion. We should really not do that ever again.<br>
<br>
<br>
<o:p></o:p></p>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<pre>Need to say, kfd SVM represent a shared virtual address space across CPU and all GPU devices on the system. This is by the definition of SVM (shared virtual memory). This is very different from our legacy gpu *device* driver which works for only one device (i.e., if you want one device to access another device's memory, you will have to use dma-buf export/import etc).<o:p></o:p></pre>
</blockquote>
<p class="MsoNormal"><br>
Exactly that thinking is what we have currently found as blocker for a virtualization projects. Having SVM as device independent feature which somehow ties to the process address space turned out to be an extremely bad idea.<br>
<br>
The background is that this only works for some use cases but not all of them.<br>
<br>
What's working much better is to just have a mirror functionality which says that a range A..B of the process address space is mapped into a range C..D of the GPU address space.<br>
<br>
Those ranges can then be used to implement the SVM feature required for higher level APIs and not something you need at the UAPI or even inside the low level kernel memory management.<br>
<br>
When you talk about migrating memory to a device you also do this on a per device basis and *not* tied to the process address space. If you then get crappy performance because userspace gave contradicting information where to migrate memory then that's a bug
in userspace and not something the kernel should try to prevent somehow.<br>
<br>
[SNIP]<br>
<br>
<o:p></o:p></p>
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<blockquote style="margin-top:5.0pt;margin-bottom:5.0pt">
<pre>I think if you start using the same drm_gpuvm for multiple devices you<o:p></o:p></pre>
<pre>will sooner or later start to run into the same mess we have seen with<o:p></o:p></pre>
<pre>KFD, where we moved more and more functionality from the KFD to the DRM<o:p></o:p></pre>
<pre>render node because we found that a lot of the stuff simply doesn't work<o:p></o:p></pre>
<pre>correctly with a single object to maintain the state.<o:p></o:p></pre>
</blockquote>
<pre><o:p> </o:p></pre>
<pre>As I understand it, KFD is designed to work across devices. A single pseudo /dev/kfd device represent all hardware gpu devices. That is why during kfd open, many pdd (process device data) is created, each for one hardware device for this process.<o:p></o:p></pre>
</blockquote>
<p class="MsoNormal"><br>
Yes, I'm perfectly aware of that. And I can only repeat myself that I see this design as a rather extreme failure. And I think it's one of the reasons why NVidia is so dominant with Cuda.<br>
<br>
This whole approach KFD takes was designed with the idea of extending the CPU process into the GPUs, but this idea only works for a few use cases and is not something we should apply to drivers in general.<br>
<br>
A very good example are virtualization use cases where you end up with CPU address != GPU address because the VAs are actually coming from the guest VM and not the host process.<br>
<br>
SVM is a high level concept of OpenCL, Cuda, ROCm etc.. This should not have any influence on the design of the kernel UAPI.<br>
<br>
If you want to do something similar as KFD for Xe I think you need to get explicit permission to do this from Dave and Daniel and maybe even Linus.<br>
<br>
Regards,<br>
Christian.<o:p></o:p></p>
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