<html><body><p> <pre> Hi, Hsiao-chien: On Thu, 2024-02-15 at 18:11 +0800, Hsiao Chien Sung wrote: > Support "Pre-multiplied" and "None" blend mode on MediaTek's chips. > Before this patch, only the "Coverage" mode is supported. > > Please refer to the description of the commit > "drm/mediatek: Support alpha blending in display driver" > for more information. Separate this patch into pre-multiplied patch and none patch. Regards, CK > > Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 83 +++++++++++++++++++++ > ---- > 1 file changed, 72 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index c42fce38a35eb..98c989fddcc08 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -39,6 +39,7 @@ > #define DISP_REG_OVL_PITCH_MSB(n)(0x0040 + 0x20 * (n)) > #define OVL_PITCH_MSB_2ND_SUBBUFBIT(16) > #define DISP_REG_OVL_PITCH(n)(0x0044 + 0x20 > * (n)) > +#define OVL_CONST_BLENDBIT(28) > #define DISP_REG_OVL_RDMA_CTRL(n)(0x00c0 + 0x20 * (n)) > #define DISP_REG_OVL_RDMA_GMC(n)(0x00c8 + 0x20 * (n)) > #define DISP_REG_OVL_ADDR_MT27010x0040 > @@ -52,13 +53,16 @@ > #define GMC_THRESHOLD_HIGH((1 << GMC_THRESHOLD_BITS) / 4) > #define GMC_THRESHOLD_LOW((1 << GMC_THRESHOLD_BITS) / 8) > > +#define OVL_CON_CLRFMT_MANBIT(23) > #define OVL_CON_BYTE_SWAPBIT(24) > -#define OVL_CON_MTX_YUV_TO_RGB(6 << 16) > +#define OVL_CON_RGB_SWAPBIT(25) > #define OVL_CON_CLRFMT_RGB(1 << 12) > #define OVL_CON_CLRFMT_RGBA8888(2 << 12) > #define OVL_CON_CLRFMT_ARGB8888(3 << 12) > #define OVL_CON_CLRFMT_UYVY(4 << 12) > #define OVL_CON_CLRFMT_YUYV(5 << 12) > +#define OVL_CON_MTX_YUV_TO_RGB(6 << 16) > +#define OVL_CON_CLRFMT_PARGB8888(OVL_CON_CLRFMT_ARGB8888 | > OVL_CON_CLRFMT_MAN) > #define OVL_CON_CLRFMT_RGB565(ovl)((ovl)->data->fmt_rgb565_is_0 ? > \ > 0 : OVL_CON_CLRFMT_RGB) > #define OVL_CON_CLRFMT_RGB888(ovl)((ovl)->data->fmt_rgb565_is_0 ? > \ > @@ -72,6 +76,22 @@ > #defineOVL_CON_VIRT_FLIPBIT(9) > #defineOVL_CON_HORZ_FLIPBIT(10) > > +static inline bool is_10bit_rgb(u32 fmt) > +{ > +switch (fmt) { > +case DRM_FORMAT_XRGB2101010: > +case DRM_FORMAT_ARGB2101010: > +case DRM_FORMAT_RGBX1010102: > +case DRM_FORMAT_RGBA1010102: > +case DRM_FORMAT_XBGR2101010: > +case DRM_FORMAT_ABGR2101010: > +case DRM_FORMAT_BGRX1010102: > +case DRM_FORMAT_BGRA1010102: > +return true; > +} > +return false; > +} > + > static const u32 mt8173_formats[] = { > DRM_FORMAT_XRGB8888, > DRM_FORMAT_ARGB8888, > @@ -89,12 +109,20 @@ static const u32 mt8173_formats[] = { > static const u32 mt8195_formats[] = { > DRM_FORMAT_XRGB8888, > DRM_FORMAT_ARGB8888, > +DRM_FORMAT_XRGB2101010, > DRM_FORMAT_ARGB2101010, > DRM_FORMAT_BGRX8888, > DRM_FORMAT_BGRA8888, > +DRM_FORMAT_BGRX1010102, > DRM_FORMAT_BGRA1010102, > DRM_FORMAT_ABGR8888, > DRM_FORMAT_XBGR8888, > +DRM_FORMAT_XBGR2101010, > +DRM_FORMAT_ABGR2101010, > +DRM_FORMAT_RGBX8888, > +DRM_FORMAT_RGBA8888, > +DRM_FORMAT_RGBX1010102, > +DRM_FORMAT_RGBA1010102, > DRM_FORMAT_RGB888, > DRM_FORMAT_BGR888, > DRM_FORMAT_RGB565, > @@ -254,9 +282,7 @@ static void mtk_ovl_set_bit_depth(struct device > *dev, int idx, u32 format, > reg = readl(ovl->regs + DISP_REG_OVL_CLRFMT_EXT); > reg &= ~OVL_CON_CLRFMT_BIT_DEPTH_MASK(idx); > > -if (format == DRM_FORMAT_RGBA1010102 || > - format == DRM_FORMAT_BGRA1010102 || > - format == DRM_FORMAT_ARGB2101010) > +if (is_10bit_rgb(format)) > bit_depth = OVL_CON_CLRFMT_10_BIT; > > reg |= OVL_CON_CLRFMT_BIT_DEPTH(bit_depth, idx); > @@ -274,7 +300,13 @@ void mtk_ovl_config(struct device *dev, unsigned > int w, > if (w != 0 && h != 0) > mtk_ddp_write_relaxed(cmdq_pkt, h << 16 | w, &ovl- > >cmdq_reg, ovl->regs, > DISP_REG_OVL_ROI_SIZE); > -mtk_ddp_write_relaxed(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, > DISP_REG_OVL_ROI_BGCLR); > + > +/* > + * The background color should be opaque black (ARGB), > + * otherwise there will be no effect with alpha blend > + */ > +mtk_ddp_write_relaxed(cmdq_pkt, 0xff000000, &ovl->cmdq_reg, > + ovl->regs, DISP_REG_OVL_ROI_BGCLR); > > mtk_ddp_write(cmdq_pkt, 0x1, &ovl->cmdq_reg, ovl->regs, > DISP_REG_OVL_RST); > mtk_ddp_write(cmdq_pkt, 0x0, &ovl->cmdq_reg, ovl->regs, > DISP_REG_OVL_RST); > @@ -352,7 +384,8 @@ void mtk_ovl_layer_off(struct device *dev, > unsigned int idx, > DISP_REG_OVL_RDMA_CTRL(idx)); > } > > -static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, > unsigned int fmt) > +static unsigned int ovl_fmt_convert(struct mtk_disp_ovl *ovl, > unsigned int fmt, > + unsigned int blend_mode) > { > /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX" > * is defined in mediatek HW data sheet. > @@ -371,17 +404,37 @@ static unsigned int ovl_fmt_convert(struct > mtk_disp_ovl *ovl, unsigned int fmt) > return OVL_CON_CLRFMT_RGB888(ovl) | OVL_CON_BYTE_SWAP; > case DRM_FORMAT_RGBX8888: > case DRM_FORMAT_RGBA8888: > +return blend_mode == DRM_MODE_BLEND_COVERAGE ? > + OVL_CON_CLRFMT_ARGB8888 : > + OVL_CON_CLRFMT_PARGB8888; > +case DRM_FORMAT_RGBX1010102: > +case DRM_FORMAT_RGBA1010102: > return OVL_CON_CLRFMT_ARGB8888; > case DRM_FORMAT_BGRX8888: > case DRM_FORMAT_BGRA8888: > +return OVL_CON_BYTE_SWAP | > + (blend_mode == DRM_MODE_BLEND_COVERAGE ? > + OVL_CON_CLRFMT_ARGB8888 : > + OVL_CON_CLRFMT_PARGB8888); > +case DRM_FORMAT_BGRX1010102: > case DRM_FORMAT_BGRA1010102: > return OVL_CON_CLRFMT_ARGB8888 | OVL_CON_BYTE_SWAP; > case DRM_FORMAT_XRGB8888: > case DRM_FORMAT_ARGB8888: > +return blend_mode == DRM_MODE_BLEND_COVERAGE ? > + OVL_CON_CLRFMT_RGBA8888 : > + OVL_CON_CLRFMT_PARGB8888; > +case DRM_FORMAT_XRGB2101010: > case DRM_FORMAT_ARGB2101010: > return OVL_CON_CLRFMT_RGBA8888; > case DRM_FORMAT_XBGR8888: > case DRM_FORMAT_ABGR8888: > +return OVL_CON_RGB_SWAP | > + (blend_mode == DRM_MODE_BLEND_COVERAGE ? > + OVL_CON_CLRFMT_RGBA8888 : > + OVL_CON_CLRFMT_PARGB8888); > +case DRM_FORMAT_XBGR2101010: > +case DRM_FORMAT_ABGR2101010: > return OVL_CON_CLRFMT_RGBA8888 | OVL_CON_BYTE_SWAP; > case DRM_FORMAT_UYVY: > return OVL_CON_CLRFMT_UYVY | OVL_CON_MTX_YUV_TO_RGB; > @@ -403,6 +456,8 @@ void mtk_ovl_layer_config(struct device *dev, > unsigned int idx, > unsigned int fmt = pending->format; > unsigned int offset = (pending->y << 16) | pending->x; > unsigned int src_size = (pending->height << 16) | pending- > >width; > +unsigned int blend_mode = state->base.pixel_blend_mode; > +unsigned int ignore_pixel_alpha = 0; > unsigned int con; > bool is_afbc = pending->modifier != DRM_FORMAT_MOD_LINEAR; > union overlay_pitch { > @@ -420,9 +475,15 @@ void mtk_ovl_layer_config(struct device *dev, > unsigned int idx, > return; > } > > -con = ovl_fmt_convert(ovl, fmt); > -if (state->base.fb && state->base.fb->format->has_alpha) > -con |= OVL_CON_AEN | OVL_CON_ALPHA; > +con = ovl_fmt_convert(ovl, fmt, blend_mode); > +if (state->base.fb) { > +con |= OVL_CON_AEN; > +con |= state->base.alpha & OVL_CON_ALPHA; > +} > + > +if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE || > + (state->base.fb && !state->base.fb->format->has_alpha)) > +ignore_pixel_alpha = OVL_CONST_BLEND; > > if (pending->rotation & DRM_MODE_REFLECT_Y) { > con |= OVL_CON_VIRT_FLIP; > @@ -439,8 +500,8 @@ void mtk_ovl_layer_config(struct device *dev, > unsigned int idx, > > mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs, > DISP_REG_OVL_CON(idx)); > -mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb, > &ovl->cmdq_reg, ovl->regs, > - DISP_REG_OVL_PITCH(idx)); > +mtk_ddp_write_relaxed(cmdq_pkt, overlay_pitch.split_pitch.lsb | > ignore_pixel_alpha, > + &ovl->cmdq_reg, ovl->regs, > DISP_REG_OVL_PITCH(idx)); > mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl- > >regs, > DISP_REG_OVL_SRC_SIZE(idx)); > mtk_ddp_write_relaxed(cmdq_pkt, offset, &ovl->cmdq_reg, ovl- > >regs, </pre> </p></body></html><pre>************* MEDIATEK Confidentiality Notice ******************** The information contained in this e-mail message (including any attachments) may be confidential, proprietary, privileged, or otherwise exempt from disclosure under applicable laws. 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