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Hi, Shawn:
On Thu, 2024-06-06 at 17:26 +0800, Shawn Sung wrote:
> From: Hsiao Chien Sung <shawn.sung@mediatek.com>
>
> Support "Pre-multiplied" alpha blending mode in Mixer.
> Before this patch, only the coverage mode is supported.
>
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_ethdr.c | 13 +++++++++----
> 1 file changed, 9 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_ethdr.c b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> index bcced62e455d..d01f65819816 100644
> --- a/drivers/gpu/drm/mediatek/mtk_ethdr.c
> +++ b/drivers/gpu/drm/mediatek/mtk_ethdr.c
> @@ -6,6 +6,7 @@
> #include <drm/drm_blend.h>
> #include <drm/drm_fourcc.h>
> #include <drm/drm_framebuffer.h>
> +#include <drm/drm_blend.h>
> #include <linux/clk.h>
> #include <linux/component.h>
> #include <linux/of.h>
> @@ -36,6 +37,7 @@
> #define MIX_SRC_L0_ENBIT(0)
> #define MIX_L_SRC_CON(n)(0x28 + 0x18 * (n))
> #define NON_PREMULTI_SOURCE(2 << 12)
> +#define PREMULTI_SOURCE(3 << 12)
> #define MIX_L_SRC_SIZE(n)(0x30 + 0x18 * (n))
> #define MIX_L_SRC_OFFSET(n)(0x34 + 0x18 * (n))
> #define MIX_FUNC_DCM00x120
> @@ -172,8 +174,12 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> return;
> }
>
> -if (state->base.fb && state->base.fb->format->has_alpha)
> -alpha_con = MIXER_ALPHA_AEN | MIXER_ALPHA;
> +alpha_con |= MIXER_ALPHA_AEN | (state->base.alpha & MIXER_ALPHA);
This is constant alpha, not related to pre-multiplied alpha, so separate it to another patch.
Regards,
CK
> +
> +if (state->base.pixel_blend_mode != DRM_MODE_BLEND_COVERAGE)
> +alpha_con |= PREMULTI_SOURCE;
> +else
> +alpha_con |= NON_PREMULTI_SOURCE;
>
> if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
> (state->base.fb && !state->base.fb->format->has_alpha)) {
> @@ -191,8 +197,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
> mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
> mixer->regs, MIX_L_SRC_SIZE(idx));
> mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
> -mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
> - 0x1ff);
> +mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));
> mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
> BIT(idx));
> }
</pre>
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