<div dir="ltr"><div dir="ltr">On Fri, Sep 6, 2024 at 6:05 AM Jocelyn Falempe <<a href="mailto:jfalempe@redhat.com">jfalempe@redhat.com</a>> wrote:<br></div><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Add drm_panic support, for nv50+ cards.<br>
It's enough to get the panic screen while running Gnome/Wayland on a<br>
GTX 1650.<br>
It doesn't support multi-plane or compressed format.<br>
Support for other formats and older cards will come later.<br>
Tiling is only tested on GTX1650, and might be wrong for other cards.<br></blockquote><div><br></div><div>I'm moderately sure that nv50 and nvc0 tile differently (the general algo is the same, but height is different):</div><div><br></div><div><a href="https://envytools.readthedocs.io/en/latest/hw/memory/g80-surface.html?highlight=tiling#blocklinear-surfaces">https://envytools.readthedocs.io/en/latest/hw/memory/g80-surface.html?highlight=tiling#blocklinear-surfaces</a><br></div><div><br></div><div>That said, I don't know that nv50 supports scanout of tiled surfaces (nor was I aware that nvc0+ did, perhaps it's a recent feature, or perhaps I'm just forgetful).</div><div><br></div><div>Cheers,</div><div><br></div><div> -ilia</div><div> </div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">
<br>
Signed-off-by: Jocelyn Falempe <<a href="mailto:jfalempe@redhat.com" target="_blank">jfalempe@redhat.com</a>><br>
---<br>
v2:<br>
* Rebase and drop already merged patches.<br>
* Rework the tiling algorithm, using "swizzle" to compute the offset<br>
inside the block.<br>
<br>
drivers/gpu/drm/nouveau/dispnv50/wndw.c | 107 +++++++++++++++++++++++-<br>
1 file changed, 105 insertions(+), 2 deletions(-)<br>
<br>
diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c<br>
index 7a2cceaee6e9..50ecf6f12b81 100644<br>
--- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c<br>
+++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c<br>
@@ -30,11 +30,16 @@<br>
#include <nvhw/class/cl507e.h><br>
#include <nvhw/class/clc37e.h><br>
<br>
+#include <linux/iosys-map.h><br>
+<br>
#include <drm/drm_atomic.h><br>
#include <drm/drm_atomic_helper.h><br>
#include <drm/drm_blend.h><br>
-#include <drm/drm_gem_atomic_helper.h><br>
#include <drm/drm_fourcc.h><br>
+#include <drm/drm_framebuffer.h><br>
+#include <drm/drm_gem_atomic_helper.h><br>
+#include <drm/drm_panic.h><br>
+#include <drm/ttm/ttm_bo.h><br>
<br>
#include "nouveau_bo.h"<br>
#include "nouveau_gem.h"<br>
@@ -577,6 +582,93 @@ nv50_wndw_prepare_fb(struct drm_plane *plane, struct drm_plane_state *state)<br>
return 0;<br>
}<br>
<br>
+#define NV_TILE_BLK_BASE_HEIGHT 8 /* In pixel */<br>
+#define NV_TILE_GOB_SIZE 64 /* In bytes */<br>
+#define NV_TILE_BLK_WIDTH (NV_TILE_GOB_SIZE / 4) /* For 32 bits pixel */<br>
+<br>
+/* get the offset in bytes inside the framebuffer, after taking tiling into account */<br>
+static unsigned int nv50_get_tiled_offset(struct drm_scanout_buffer *sb, unsigned int blk_h,<br>
+ unsigned int x, unsigned int y)<br>
+{<br>
+ u32 blk_x, blk_y, blk_sz, blk_off, pitch;<br>
+ u32 swizzle;<br>
+<br>
+ blk_sz = NV_TILE_GOB_SIZE * blk_h;<br>
+ pitch = DIV_ROUND_UP(sb->width, NV_TILE_BLK_WIDTH);<br>
+<br>
+ /* block coordinate */<br>
+ blk_x = x / NV_TILE_BLK_WIDTH;<br>
+ blk_y = y / blk_h;<br>
+<br>
+ blk_off = ((blk_y * pitch) + blk_x) * blk_sz;<br>
+<br>
+ y = y % blk_h;<br>
+<br>
+ /* Inside the block, use the fast address swizzle to compute the offset<br>
+ * For nvidia blocklinear, bit order is yn..y3 x3 y2 x2 y1 y0 x1 x0<br>
+ */<br>
+ swizzle = (x & 3) | (y & 3) << 2 | (x & 4) << 2 | (y & 4) << 3;<br>
+ swizzle |= (x & 8) << 3 | (y >> 3) << 7;<br>
+<br>
+ return blk_off + swizzle * 4;<br>
+}<br>
+<br>
+static void nv50_set_pixel(struct drm_scanout_buffer *sb, unsigned int x, unsigned int y, u32 color)<br>
+{<br>
+ struct drm_framebuffer *fb = sb->private;<br>
+ unsigned int off;<br>
+ /* According to DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D documentation,<br>
+ * the last 4 bits of the modifier is log2(blk_height / NV_TILE_BLK_BASE_HEIGHT)<br>
+ */<br>
+ unsigned int blk_h = NV_TILE_BLK_BASE_HEIGHT * (1 << (fb->modifier & 0xf));<br>
+<br>
+ off = nv50_get_tiled_offset(sb, blk_h, x, y);<br>
+ iosys_map_wr(&sb->map[0], off, u32, color);<br>
+}<br>
+<br>
+static int<br>
+nv50_wndw_get_scanout_buffer(struct drm_plane *plane, struct drm_scanout_buffer *sb)<br>
+{<br>
+ struct drm_framebuffer *fb;<br>
+ struct nouveau_bo *nvbo;<br>
+<br>
+ if (!plane->state || !plane->state->fb)<br>
+ return -EINVAL;<br>
+<br>
+ fb = plane->state->fb;<br>
+ nvbo = nouveau_gem_object(fb->obj[0]);<br>
+<br>
+ /* Don't support compressed format, or multiplane yet. */<br>
+ if (nvbo->comp || fb->format->num_planes != 1)<br>
+ return -EOPNOTSUPP;<br>
+<br>
+ if (nouveau_bo_map(nvbo)) {<br>
+ pr_warn("nouveau bo map failed, panic won't be displayed\n");<br>
+ return -ENOMEM;<br>
+ }<br>
+<br>
+ if (nvbo->kmap.bo_kmap_type & TTM_BO_MAP_IOMEM_MASK)<br>
+ iosys_map_set_vaddr_iomem(&sb->map[0], nvbo->kmap.virtual);<br>
+ else<br>
+ iosys_map_set_vaddr(&sb->map[0], nvbo->kmap.virtual);<br>
+<br>
+ sb->height = fb->height;<br>
+ sb->width = fb->width;<br>
+ sb->pitch[0] = fb->pitches[0];<br>
+ sb->format = fb->format;<br>
+<br>
+ /* If tiling is enabled, use the set_pixel() to display correctly.<br>
+ * Only handle 32bits format for now.<br>
+ */<br>
+ if (fb->modifier & 0xf) {<br>
+ if (fb->format->cpp[0] != 4)<br>
+ return -EOPNOTSUPP;<br>
+ sb->private = (void *) fb;<br>
+ sb->set_pixel = nv50_set_pixel;<br>
+ }<br>
+ return 0;<br>
+}<br>
+<br>
static const struct drm_plane_helper_funcs<br>
nv50_wndw_helper = {<br>
.prepare_fb = nv50_wndw_prepare_fb,<br>
@@ -584,6 +676,14 @@ nv50_wndw_helper = {<br>
.atomic_check = nv50_wndw_atomic_check,<br>
};<br>
<br>
+static const struct drm_plane_helper_funcs<br>
+nv50_wndw_primary_helper = {<br>
+ .prepare_fb = nv50_wndw_prepare_fb,<br>
+ .cleanup_fb = nv50_wndw_cleanup_fb,<br>
+ .atomic_check = nv50_wndw_atomic_check,<br>
+ .get_scanout_buffer = nv50_wndw_get_scanout_buffer,<br>
+};<br>
+<br>
static void<br>
nv50_wndw_atomic_destroy_state(struct drm_plane *plane,<br>
struct drm_plane_state *state)<br>
@@ -732,7 +832,10 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev,<br>
return ret;<br>
}<br>
<br>
- drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);<br>
+ if (type == DRM_PLANE_TYPE_PRIMARY)<br>
+ drm_plane_helper_add(&wndw->plane, &nv50_wndw_primary_helper);<br>
+ else<br>
+ drm_plane_helper_add(&wndw->plane, &nv50_wndw_helper);<br>
<br>
if (wndw->func->ilut) {<br>
ret = nv50_lut_init(disp, mmu, &wndw->ilut);<br>
-- <br>
2.46.0<br>
<br>
</blockquote></div></div>