<html><body><p>
<pre>
Hi, Shu-hsiang:
On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---
[snip]
> +static bool mtk_cam_raw_resource_calc(struct mtk_cam_device *cam,
> + struct mtk_cam_resource_config *res,
> + s64 pixel_rate, int res_plan,
> + int in_w, int in_h, int *out_w, int *out_h)
> +{
> +int res_step_type = 0;
> +int tgo_pxl_mode = 1;
> +int pixel_mode[MTK_CAMSYS_RES_STEP_NUM] = {0};
> +int bin_temp = 0, frz_temp = 0, hwn_temp = 0;
> +int bin_en = 0, frz_en = 0, twin_en = 0, clk_cur = 0;
> +int idx = 0, clk_res = 0, idx_res = 0;
> +bool res_found = false;
> +int lb_chk_res = -1;
> +int frz_ratio = 100;
> +int p;
> +
> +res->res_plan = res_plan;
> +res->pixel_rate = pixel_rate;
> +/* test pattern */
> +if (res->pixel_rate == 0)
> +res->pixel_rate = 450 * MHz;
> +dev_dbg(cam->dev,
> +"[Res] PR = %lld, w/h=%d/%d HWN(%d)/BIN(%d)/FRZ(%d),Plan:%d\n",
> +res->pixel_rate, in_w, in_h,
> +res->hwn_limit_max, res->bin_limit, res->frz_limit, res->res_plan);
> +
> +memcpy(res->res_strategy, raw_resource_strategy_plan + res->res_plan,
> + MTK_CAMSYS_RES_STEP_NUM * sizeof(int));
> +res->bin_enable = 0;
> +res->raw_num_used = 1;
> +res->frz_enable = 0;
> +res->frz_ratio = frz_ratio;
> +for (idx = 0; idx < MTK_CAMSYS_RES_STEP_NUM ; idx++) {
> +res_step_type = res->res_strategy[idx] & MTK_CAMSYS_RES_IDXMASK;
> +switch (res_step_type) {
> +case MTK_CAMSYS_RES_BIN_TAG:
> +bin_temp = res->res_strategy[idx] - E_RES_BIN_S;
> +if (bin_temp <= res->bin_limit)
> +bin_en = bin_temp;
> +if (bin_en && frz_en)
> +frz_en = 0;
> +break;
> +case MTK_CAMSYS_RES_FRZ_TAG:
> +frz_temp = res->res_strategy[idx] - E_RES_FRZ_S;
> +if (res->frz_limit < 100)
> +frz_en = frz_temp;
> +break;
> +case MTK_CAMSYS_RES_HWN_TAG:
> +hwn_temp = res->res_strategy[idx] - E_RES_HWN_S;
> +if (hwn_temp + 1 <= res->hwn_limit_max)
> +twin_en = hwn_temp;
> +break;
> +case MTK_CAMSYS_RES_CLK_TAG:
> +clk_cur = res->res_strategy[idx] - E_RES_CLK_S;
> +break;
> +default:
> +break;
> +}
> +
> +/* 1 for force bin on */
> +if (res->bin_limit >= 1)
> +bin_en = 1;
> +
> +if (res->hwn_limit_min > 1)
> +twin_en = 1;
> +
> +/* max line buffer check*/
> +lb_chk_res = mtk_raw_linebuf_chk(twin_en, res->bin_limit & BIN_ON,
> + frz_en, res->bin_limit & QBND_ON,
> + is_cbn_en(res->bin_limit),
> + in_w, &frz_ratio);
> +/* frz ratio*/
> +if (res_step_type == MTK_CAMSYS_RES_FRZ_TAG) {
> +res->frz_ratio = res->frz_limit < FRZ_PXLMODE_THRES ?
> +res->frz_limit : FRZ_PXLMODE_THRES;
> +}
> +/*try 1-pixel mode first*/
> +for (p = 1; p <= MTK_CAMSYS_PROC_DEFAULT_PIXELMODE; p++) {
MTK_CAMSYS_PROC_DEFAULT_PIXELMODE is 1, so this for-loop could be dropped.
> +tgo_pxl_mode = mtk_raw_pixelmode_calc(p, twin_en,
> + bin_en, frz_en,
> + res->frz_ratio);
mtk_raw_pixelmode_calc() would always return 1, so mtk_raw_pixelmode_calc() could be dropped.
Regards,
CK
> +/**
> + * isp throughput along resource strategy
> + * (compared with pixel rate)
> + */
> +pixel_mode[idx] = tgo_pxl_mode;
> +
> +/* only support 1-pixel mode */
> +if (p == 1 && lb_chk_res == LB_CHECK_OK) {
> +if (!res_found) {
> +res->bin_enable = bin_en;
> +res->frz_enable = frz_en;
> +res->raw_num_used = twin_en + 1;
> +clk_res = clk_cur;
> +idx_res = idx;
> +res_found = true;
> +break;
> +}
> +}
> +}
> +dev_dbg(cam->dev,
> +"Res-%d B/F/H/C=%d/%d/%d/%d -> %d/%d/%d/%d (%d)(%d)\n",
> +idx, bin_temp, frz_temp, hwn_temp, clk_cur, bin_en,
> +frz_en, twin_en, clk_cur, lb_chk_res, pixel_mode[idx]);
> +}
> +
> +tgo_pxl_mode = pixel_mode[idx_res];
> +switch (tgo_pxl_mode) {
> +case 1:
> +res->tgo_pxl_mode = 0;
> +break;
> +case 2:
> +res->tgo_pxl_mode = 1;
> +break;
> +case 4:
> +res->tgo_pxl_mode = 2;
> +break;
> +case 8:
> +res->tgo_pxl_mode = 3;
> +break;
> +default:
> +break;
> +}
> +
> +mtk_raw_update_debug_param(cam, res, &clk_res);
> +
> +if (res_found) {
> +dev_info(cam->dev,
> + "Res-end:%d BIN/FRZ/HWN/CLK/pxl=%d/%d(%d)/%d/%d/%d, clk:%d\n",
> + idx_res, res->bin_enable, res->frz_enable, res->frz_ratio,
> + res->raw_num_used, clk_res, res->tgo_pxl_mode,
> + res->clk_target);
> +} else {
> +dev_dbg(cam->dev, "[%s] Error resource result\n", __func__);
> +}
> +if (res->bin_enable) {
> +*out_w = in_w >> 1;
> +*out_h = in_h >> 1;
> +} else if (res->frz_enable) {
> +*out_w = in_w * res->frz_ratio / 100;
> +*out_h = in_h * res->frz_ratio / 100;
> +} else {
> +*out_w = in_w;
> +*out_h = in_h;
> +}
> +
> +return res_found;
> +}
> +
</pre>
</p></body></html><!--type:text--><!--{--><pre>************* MEDIATEK Confidentiality Notice ********************
The information contained in this e-mail message (including any
attachments) may be confidential, proprietary, privileged, or otherwise
exempt from disclosure under applicable laws. It is intended to be
conveyed only to the designated recipient(s). Any use, dissemination,
distribution, printing, retaining or copying of this e-mail (including its
attachments) by unintended recipient(s) is strictly prohibited and may
be unlawful. If you are not an intended recipient of this e-mail, or believe
that you have received this e-mail in error, please notify the sender
immediately (by replying to this e-mail), delete any and all copies of
this e-mail (including any attachments) from your system, and do not
disclose the content of this e-mail to any other person. Thank you!
</pre><!--}-->