<html><body><p> <pre> Hi, Shu-hsiang: On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote: > Introduces support for the sensor interface in the MediaTek SoC, > with the focus on CSI and stream control. The key functionalities > include parameter control, metering and maintaining status information, > interrupt handling, and debugging. These features ensure effective > management and debugging of the camera sensor interface hardware. > > Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com> > --- [snip] > + > +#define SENINF_CAM_MUX0_CHK_CTL_1 0x0104 > +#define RG_SENINF_CAM_MUX0_EXP_HSIZE_SHIFT 0 > +#define RG_SENINF_CAM_MUX0_EXP_HSIZE_MASK (0xffff << 0) > +#define RG_SENINF_CAM_MUX0_EXP_VSIZE_SHIFT 16 > +#define RG_SENINF_CAM_MUX0_EXP_VSIZE_MASK (0xffff << 16) #define SENINF_CAM_MUX_CHK_CTL_1(n)(0x0104 + 0x10 * n) #define RG_SENINF_CAM_MUX_EXP_HSIZE_SHIFT 0 #define RG_SENINF_CAM_MUX_EXP_HSIZE_MASK (0xffff << 0) #define RG_SENINF_CAM_MUX_EXP_VSIZE_SHIFT 16 #define RG_SENINF_CAM_MUX_EXP_VSIZE_MASK (0xffff << 16) > +int mtk_cam_seninf_set_cammux_src(struct seninf_ctx *ctx, int src, > + int target, int exp_hsize, int exp_vsize) > +{ > +void __iomem *seninf_cam_mux_base = ctx->reg_if_cam_mux; > + > [snip] > + > +switch (target) { > +case SENINF_CAM_MUX0: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_0, > + RG_SENINF_CAM_MUX0_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX0_CHK_CTL_1, > + RG_SENINF_CAM_MUX0_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX0_CHK_CTL_1, > + RG_SENINF_CAM_MUX0_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX1: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_0, > + RG_SENINF_CAM_MUX1_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX1_CHK_CTL_1, > + RG_SENINF_CAM_MUX1_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX1_CHK_CTL_1, > + RG_SENINF_CAM_MUX1_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX2: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_0, > + RG_SENINF_CAM_MUX2_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX2_CHK_CTL_1, > + RG_SENINF_CAM_MUX2_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX2_CHK_CTL_1, > + RG_SENINF_CAM_MUX2_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX3: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_0, > + RG_SENINF_CAM_MUX3_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX3_CHK_CTL_1, > + RG_SENINF_CAM_MUX3_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX3_CHK_CTL_1, > + RG_SENINF_CAM_MUX3_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX4: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_1, > + RG_SENINF_CAM_MUX4_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX4_CHK_CTL_1, > + RG_SENINF_CAM_MUX4_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX4_CHK_CTL_1, > + RG_SENINF_CAM_MUX4_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX5: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_1, > + RG_SENINF_CAM_MUX5_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX5_CHK_CTL_1, > + RG_SENINF_CAM_MUX5_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX5_CHK_CTL_1, > + RG_SENINF_CAM_MUX5_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX6: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_1, > + RG_SENINF_CAM_MUX6_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX6_CHK_CTL_1, > + RG_SENINF_CAM_MUX6_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX6_CHK_CTL_1, > + RG_SENINF_CAM_MUX6_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX7: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_1, > + RG_SENINF_CAM_MUX7_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX7_CHK_CTL_1, > + RG_SENINF_CAM_MUX7_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX7_CHK_CTL_1, > + RG_SENINF_CAM_MUX7_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX8: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_2, > + RG_SENINF_CAM_MUX8_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX8_CHK_CTL_1, > + RG_SENINF_CAM_MUX8_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX8_CHK_CTL_1, > + RG_SENINF_CAM_MUX8_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX9: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_2, > + RG_SENINF_CAM_MUX9_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX9_CHK_CTL_1, > + RG_SENINF_CAM_MUX9_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX9_CHK_CTL_1, > + RG_SENINF_CAM_MUX9_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX10: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_2, > + RG_SENINF_CAM_MUX10_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX10_CHK_CTL_1, > + RG_SENINF_CAM_MUX10_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX10_CHK_CTL_1, > + RG_SENINF_CAM_MUX10_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX11: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_2, > + RG_SENINF_CAM_MUX11_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX11_CHK_CTL_1, > + RG_SENINF_CAM_MUX11_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX11_CHK_CTL_1, > + RG_SENINF_CAM_MUX11_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX12: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_3, > + RG_SENINF_CAM_MUX12_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX12_CHK_CTL_1, > + RG_SENINF_CAM_MUX12_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX12_CHK_CTL_1, > + RG_SENINF_CAM_MUX12_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX13: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_3, > + RG_SENINF_CAM_MUX13_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX13_CHK_CTL_1, > + RG_SENINF_CAM_MUX13_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX13_CHK_CTL_1, > + RG_SENINF_CAM_MUX13_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX14: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_3, > + RG_SENINF_CAM_MUX14_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX14_CHK_CTL_1, > + RG_SENINF_CAM_MUX14_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX14_CHK_CTL_1, > + RG_SENINF_CAM_MUX14_EXP_VSIZE, exp_vsize); > +break; > +case SENINF_CAM_MUX15: > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CTRL_3, > + RG_SENINF_CAM_MUX15_SRC_SEL, src); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX15_CHK_CTL_1, > + RG_SENINF_CAM_MUX15_EXP_HSIZE, exp_hsize); > +SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX15_CHK_CTL_1, > + RG_SENINF_CAM_MUX15_EXP_VSIZE, exp_vsize); > +break; > +default: > +dev_dbg(ctx->dev, "invalid src %d target %d", src, target); > +return -EINVAL; > +} Replace the switch like this: SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CHK_CTL_1(target), RG_SENINF_CAM_MUX_EXP_HSIZE, exp_hsize); SENINF_BITS(seninf_cam_mux_base, SENINF_CAM_MUX_CHK_CTL_1(target), RG_SENINF_CAM_MUX_EXP_VSIZE, exp_vsize); Regards, CK > + > +return 0; > +} > + </pre> </p></body></html><pre>************* MEDIATEK Confidentiality Notice ******************** The information contained in this e-mail message (including any attachments) may be confidential, proprietary, privileged, or otherwise exempt from disclosure under applicable laws. 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