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<pre>
Hi, Shu-hsiang:

On Wed, 2024-10-09 at 19:15 +0800, Shu-hsiang Yang wrote:
> Introduces the ISP pipeline driver for the MediaTek ISP raw and yuv
> modules. Key functionalities include data processing, V4L2 integration,
> resource management, debug support, and various control operations.
> Additionally, IRQ handling, platform device management, and MediaTek
> ISP DMA format support are also included.
>
> Signed-off-by: Shu-hsiang Yang <Shu-hsiang.Yang@mediatek.com>
> ---

[snip]

> +void mtk_cam_dump_req_rdy_status(struct device *dev,
> + void __iomem *base, void __iomem *yuvbase)
> +{

This function is useless, so drop it.

Regards,
CK

> +dev_dbg_ratelimited(dev,
> + "REQ RAW/2/3 DMA/2:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(base + REG_CTL_RAW_MOD_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD2_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD3_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD5_REQ_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD6_REQ_STAT));
> +dev_dbg_ratelimited(dev,
> + "RDY RAW/2/3 DMA/2:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(base + REG_CTL_RAW_MOD_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD2_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD3_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD5_RDY_STAT),
> + readl_relaxed(base + REG_CTL_RAW_MOD6_RDY_STAT));
> +dev_dbg_ratelimited(dev,
> + "REQ YUV/2/3/4 WDMA:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD2_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD3_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD4_REQ_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD5_REQ_STAT));
> +dev_dbg_ratelimited(dev,
> + "RDY YUV/2/3/4 WDMA:%08x/%08x/%08x/%08x/%08x\n",
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD2_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD3_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD4_RDY_STAT),
> + readl_relaxed(yuvbase + REG_CTL_RAW_MOD5_RDY_STAT));
> +}
> +


</pre>
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