<html><body><p> <pre> Hi, Angelo: On Thu, 2024-12-05 at 12:45 +0100, AngeloGioacchino Del Regno wrote: > External email : Please do not click links or open attachments until you have verified the sender or the content. > > > Add a binding for the HDMI TX v2 Encoder found in MediaTek MT8195 > and MT8188 SoCs. > > This fully supports the HDMI Specification 2.0b, hence it provides > support for 3D-HDMI, Polarity inversion, up to 16 bits Deep Color, > color spaces including RGB444, YCBCR420/422/444 (ITU601/ITU709) and > xvYCC, with output resolutions up to 3840x2160p@60Hz. > > Moreover, it also supports HDCP 1.4 and 2.3, Variable Refresh Rate > (VRR) and Consumer Electronics Control (CEC). > > This IP also includes support for HDMI Audio, including IEC60958 > and IEC61937 SPDIF, 8-channel PCM, DSD, and other lossless audio > according to HDMI 2.0. NOTE: There is discussion in [1]. [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20241205114518.53527-8-angelogioacchino.delregno@collabora.com/ Regards, CK > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > --- > .../mediatek/mediatek,mt8195-hdmi.yaml | 154 ++++++++++++++++++ > 1 file changed, 154 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml > new file mode 100644 > index 000000000000..73b1dfaa1adb > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8195-hdmi.yaml > @@ -0,0 +1,154 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: https://urldefense.com/v3/__http://devicetree.org/schemas/display/mediatek/mediatek,mt8195-hdmi.yaml*__;Iw!!CTRNKA9wMg0ARbw!kB8f630CUolqkpX3ipvy1_HEGMcwQWXsfpv2JWDnW8CZckULvtoH-VsWFxMXeT035x4ETMcswV81yMrCH3cRsXiprSpF$ > +$schema: https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!kB8f630CUolqkpX3ipvy1_HEGMcwQWXsfpv2JWDnW8CZckULvtoH-VsWFxMXeT035x4ETMcswV81yMrCH3cRsfC96NsG$ > + > +title: MediaTek HDMI-TX v2 Encoder > + > +maintainers: > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + - CK Hu <ck.hu@mediatek.com> > + > +description: > + The MediaTek HDMI-TX v2 encoder can generate HDMI format data based on > + the HDMI Specification 2.0b. > + > +properties: > + compatible: > + enum: > + - mediatek,mt8188-hdmi-tx > + - mediatek,mt8195-hdmi-tx > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: HDMI Peripheral Bus (APB) clock > + - description: HDCP and HDMI_TOP clock > + - description: HDCP and HDMI_TOP reference clock > + - description: VPP HDMI Split clock > + > + clock-names: > + items: > + - const: bus > + - const: hdcp > + - const: hdcp24m > + - const: hdmi-split > + > + i2c: > + type: object > + $ref: /schemas/display/mediatek/mediatek,mt8195-hdmi-ddc.yaml > + unevaluatedProperties: false > + description: HDMI DDC I2C controller > + > + phys: > + maxItems: 1 > + description: PHY providing clocking TMDS and pixel to controller > + > + phy-names: > + items: > + - const: hdmi > + > + pinctrl-0: true > + > + pinctrl-names: > + items: > + - const: default > + > + power-domains: > + maxItems: 1 > + > + '#sound-dai-cells': > + const: 1 > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Input port, usually connected to the output port of a DPI > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: > + Output port that must be connected either to the input port of > + a HDMI connector node containing a ddc-i2c-bus, or to the input > + port of an attached bridge chip, such as a SlimPort transmitter. > + > + required: > + - port@0 > + - port@1 > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - power-domains > + - phys > + - phy-names > + - ports > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/mt8195-clk.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/mt8195-power.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + hdmi-tx@1c300000 { > + compatible = "mediatek,mt8195-hdmi-tx"; > + reg = <0 0x1c300000 0 0x1000>; > + clocks = <&topckgen CLK_TOP_HDMI_APB>, > + <&topckgen CLK_TOP_HDCP>, > + <&topckgen CLK_TOP_HDCP_24M>, > + <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; > + clock-names = "bus", "hdcp", "hdcp24m", "hdmi-split"; > + interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH 0>; > + phys = <&hdmi_phy>; > + phy-names = "hdmi"; > + power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>; > + pinctrl-names = "default"; > + pinctrl-0 = <&hdmi_pins>; > + #sound-dai-cells = <1>; > + > + hdmitx_ddc: i2c { > + compatible = "mediatek,mt8195-hdmi-ddc"; > + clocks = <&clk26m>; > + }; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + hdmi_in: endpoint { > + remote-endpoint = <&dpi1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + hdmi_out: endpoint { > + remote-endpoint = <&hdmi_connector_in>; > + }; > + }; > + }; > + }; > + }; > -- > 2.47.0 > </pre> </p></body></html><pre>************* MEDIATEK Confidentiality Notice ******************** The information contained in this e-mail message (including any attachments) may be confidential, proprietary, privileged, or otherwise exempt from disclosure under applicable laws. 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